Define init, txbegin, txend and txputchar macros.

[bertos.git] / cpu / cpu.h

diff --git a/cpu/cpu.h b/cpu/cpu.h
index cf79f7efd4483fbc8c8b1c11ea4f843812a3adad..1e68ac2c2d578e6deadb4e7d778ed6c62c74982d 100644 (file)
--- a/cpu/cpu.h
+++ b/cpu/cpu.h
@@ -154,7 +154,7 @@
                        set_CPSR(x); \
                } while (0)
 
-               #define IRQ_GETSTATE() \
+               #define IRQ_ENABLED() \
                        ((bool)(get_CPSR() & 0xb0))
 
                #define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
@@ -205,7 +205,7 @@
 
                #define CPU_READ_FLAGS() \
                ({ \
-                       uint32_t sreg; \
+                       cpuflags_t sreg; \
                        asm volatile ( \
                                "mrs %0, cpsr\n\t" \
                                : "=r" (sreg) \
@@ -214,16 +214,21 @@
                        sreg; \
                })
 
-               #define IRQ_GETSTATE() (!((CPU_READ_FLAGS() & 0xc0) == 0xc0))
+               #define IRQ_ENABLED() ((CPU_READ_FLAGS() & 0xc0) != 0xc0)
 
                /**
                 * Initialization value for registers in stack frame.
                 * The register index is not directly corrispondent to CPU
-                * register numbers, but is related to how are pushed to stack (\see asm_switch_context).
-                * Index (CPU_SAVED_REGS_CNT - 1) is the CPSR register:
-                * the initial value is taken from current CPSR.
+                * register numbers, but is related to how are pushed to
+                * stack (\see asm_switch_context).
+                * Index (CPU_SAVED_REGS_CNT - 1) is the CPSR register,
+                * the initial value is set to:
+                * - All flags (N, Z, C, V) set to 0.
+                * - IRQ and FIQ enabled.
+                * - ARM state.
+                * - CPU in Supervisor Mode (SVC).
                 */
-               #define CPU_REG_INIT_VALUE(reg) (reg == (CPU_SAVED_REGS_CNT - 1) ? CPU_READ_FLAGS() : 0)
+               #define CPU_REG_INIT_VALUE(reg) (reg == (CPU_SAVED_REGS_CNT - 1) ? 0x13 : 0)
 
        #endif /* !__IAR_SYSTEMS_ICC_ */
 
@@ -234,7 +239,7 @@
        #define IRQ_ENABLE          FIXME
        #define IRQ_SAVE_DISABLE(x) FIXME
        #define IRQ_RESTORE(x)      FIXME
-       #define IRQ_GETSTATE()      FIXME
+       #define IRQ_ENABLED()      FIXME
 
        typedef uint32_t cpuflags_t; // FIXME
        typedef uint32_t cpustack_t; // FIXME
@@ -267,13 +272,13 @@
        }
        #define IRQ_RUNNING() irq_running()
 
-       static inline bool irq_getstate(void)
+       static inline bool irq_enabled(void)
        {
                uint16_t x;
                asm(move SR,x);
                return !(x & 0x0200);
        }
-       #define IRQ_GETSTATE() irq_getstate()
+       #define IRQ_ENABLED() irq_enabled()
 
        typedef uint16_t cpuflags_t;
        typedef unsigned int cpustack_t;
@@ -315,7 +320,7 @@
                ); \
        } while (0)
 
-       #define IRQ_GETSTATE() \
+       #define IRQ_ENABLED() \
        ({ \
                uint8_t sreg; \
                __asm__ __volatile__( \