/*#*
*#* $Log$
+ *#* Revision 1.28 2004/12/31 17:39:41 bernie
+ *#* Fix documentation.
+ *#*
+ *#* Revision 1.27 2004/12/31 17:02:47 bernie
+ *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
+ *#*
+ *#* Revision 1.26 2004/12/13 12:08:12 bernie
+ *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
+ *#*
+ *#* Revision 1.25 2004/12/08 08:31:02 bernie
+ *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
+ *#*
+ *#* Revision 1.24 2004/12/08 08:04:13 bernie
+ *#* Doxygen fixes.
+ *#*
+ *#* Revision 1.23 2004/11/16 22:41:58 bernie
+ *#* Support 64bit CPUs.
+ *#*
+ *#* Revision 1.22 2004/11/16 21:57:59 bernie
+ *#* CPU_IDLE: Rename from SCHEDULER_IDLE.
+ *#*
+ *#* Revision 1.21 2004/11/16 21:34:25 bernie
+ *#* Commonize obsolete names for IRQ macros; Doxygen fixes.
+ *#*
+ *#* Revision 1.20 2004/11/16 20:33:32 bernie
+ *#* CPU_HARVARD: New macro.
+ *#*
*#* Revision 1.19 2004/10/03 20:43:54 bernie
*#* Fix Doxygen markup.
*#*
#ifndef DEVLIB_CPU_H
#define DEVLIB_CPU_H
-#include "compiler.h" /* for uintXX_t, PP_CAT3(), PP_STRINGIZE() */
+#include "compiler.h" /* for uintXX_t */
-// Macros for determining CPU endianness
+/*!
+ * \name Macros for determining CPU endianness.
+ * \{
+ */
#define CPU_BIG_ENDIAN 0x1234
#define CPU_LITTLE_ENDIAN 0x3412
+/*\}*/
-// Macros to include cpu-specific version of the headers
+/*! Macro to include cpu-specific versions of the headers. */
#define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
#if CPU_I196
- #define DISABLE_INTS disable_interrupt()
- #define ENABLE_INTS enable_interrupt()
#define NOP nop_instruction()
+ #define IRQ_DISABLE disable_interrupt()
+ #define IRQ_ENABLE enable_interrupt()
typedef uint16_t cpuflags_t; // FIXME
typedef unsigned int cpustack_t;
#define CPU_STACK_GROWS_UPWARD 0
#define CPU_SP_ON_EMPTY_SLOT 0
#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+ #define CPU_HARVARD 0
#elif CPU_X86
#define NOP asm volatile ("nop")
- #define DISABLE_INTS /* nothing */
- #define ENABLE_INTS /* nothing */
+ #define IRQ_DISABLE /* nothing */
+ #define IRQ_ENABLE /* nothing */
+ #define IRQ_SAVE_DISABLE(x) /* nothing */
+ #define IRQ_RESTORE(x) /* nothing */
typedef uint32_t cpuflags_t; // FIXME
typedef uint32_t cpustack_t;
#define CPU_STACK_GROWS_UPWARD 0
#define CPU_SP_ON_EMPTY_SLOT 0
#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+ #define CPU_HARVARD 0
#elif CPU_DSP56K
#define NOP asm(nop)
- #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
- #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
+ #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
+ #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
- #define DISABLE_IRQSAVE(x) \
+ #define IRQ_SAVE_DISABLE(x) \
do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
- #define ENABLE_IRQRESTORE(x) \
+ #define IRQ_RESTORE(x) \
do { (void)x; asm(move x,SR); } while (0)
+
typedef uint16_t cpuflags_t;
typedef unsigned int cpustack_t;
#define CPU_STACK_GROWS_UPWARD 1
#define CPU_SP_ON_EMPTY_SLOT 0
#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+ #define CPU_HARVARD 1
/* Memory is word-addessed in the DSP56K */
#define CPU_BITS_PER_CHAR 16
(bool)(sreg & 0x80); \
})
- /* OBSOLETE NAMES */
- #define DISABLE_INTS IRQ_DISABLE
- #define ENABLE_INTS IRQ_ENABLE
- #define DISABLE_IRQSAVE(x) IRQ_SAVE_DISABLE(x)
- #define ENABLE_IRQRESTORE(x) IRQ_RESTORE(x)
-
typedef uint8_t cpuflags_t;
typedef uint8_t cpustack_t;
#define CPU_STACK_GROWS_UPWARD 0
#define CPU_SP_ON_EMPTY_SLOT 1
#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+ #define CPU_HARVARD 1
/*!
* Initialization value for registers in stack frame.
/*!
* Execute \a CODE atomically with respect to interrupts.
*
- * \see ENABLE_IRQSAVE DISABLE_IRQRESTORE
+ * \see IRQ_SAVE_DISABLE IRQ_RESTORE
*/
#define ATOMIC(CODE) \
do { \
cpuflags_t __flags; \
- DISABLE_IRQSAVE(__flags); \
+ IRQ_SAVE_DISABLE(__flags); \
CODE; \
- ENABLE_IRQRESTORE(__flags); \
+ IRQ_RESTORE(__flags); \
} while (0)
#if CPU_DSP56K
- /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
+ /*
+ * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
* RTS discards SR while returning (it does not restore it). So we push
* 0 to fake the same context.
*/
} while (0);
#elif CPU_AVR
- /* In AVR, the addresses are pushed into the stack as little-endian, while
+ /*
+ * In AVR, the addresses are pushed into the stack as little-endian, while
* memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
* no natural endianess).
*/
/*!
- * \name Default type sizes
- *
- * \def SIZEOF_CHAR SIZEOF_SHORT SIZEOF_INT SIZEOF_LONG SIZEOF_PTR
- * \def CPU_BITS_PER_CHAR CPU_BITS_PER_SHORT CPU_BITS_PER_INT
- * \def CPU_BITS_PER_LONG CPU_BITS_PER_PTR
+ * \name Default type sizes.
*
* These defaults are reasonable for most 16/32bit machines.
* Some of these macros may be overridden by CPU-specific code above.
#endif /* !SIZEOF_INT */
#ifndef SIZEOF_LONG
-#define SIZEOF_LONG 4
+#if CPU_REG_BITS > 32
+ #define SIZEOF_LONG 8
+#else
+ #define SIZEOF_LONG 4
+#endif
#endif
#ifndef SIZEOF_PTR
/*!
- * \def SCHEDULER_IDLE
+ * \def CPU_IDLE
*
* \brief Invoked by the scheduler to stop the CPU when idle.
*
* profile system load with an external strobe, or to save CPU cycles
* in hosted environments such as emulators.
*/
-#ifndef SCHEDULER_IDLE
+#ifndef CPU_IDLE
#if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
/* This emulator hook should yield the CPU to the host. */
EXTERN_C_BEGIN
void SchedulerIdle(void);
EXTERN_C_END
- #define SCHEDULER_IDLE SchedulerIdle()
+ #define CPU_IDLE SchedulerIdle()
#else /* !ARCH_EMUL */
- #define SCHEDULER_IDLE do { /* nothing */ } while (0)
+ #define CPU_IDLE do { /* nothing */ } while (0)
#endif /* !ARCH_EMUL */
-#endif /* !SCHEDULER_IDLE */
+#endif /* !CPU_IDLE */
+
+/* OBSOLETE */
+#define SCHEDULER_IDLE CPU_IDLE
#endif /* DEVLIB_CPU_H */
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