/*!
* \file
* <!--
- * Copyright 2004 Develer S.r.l. (http://www.develer.com/)
+ * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
* Copyright 2004 Giovanni Bajo
- * This file is part of DevLib - See devlib/README for information.
+ * This file is part of DevLib - See README.devlib for information.
* -->
*
* \brief CPU-specific definitions
/*#*
*#* $Log$
- *#* Revision 1.22 2004/11/16 21:57:59 bernie
- *#* CPU_IDLE: Rename from SCHEDULER_IDLE.
+ *#* Revision 1.30 2005/03/15 00:20:09 bernie
+ *#* BREAKPOINT, IRQ_RUNNING(), IRQ_GETSTATE(): New DSP56K macros.
*#*
- *#* Revision 1.21 2004/11/16 21:34:25 bernie
- *#* Commonize obsolete names for IRQ macros; Doxygen fixes.
+ *#* Revision 1.29 2005/02/16 20:33:24 bernie
+ *#* Preliminary PPC support.
*#*
- *#* Revision 1.20 2004/11/16 20:33:32 bernie
- *#* CPU_HARVARD: New macro.
+ *#* Revision 1.28 2004/12/31 17:39:41 bernie
+ *#* Fix documentation.
*#*
- *#* Revision 1.19 2004/10/03 20:43:54 bernie
- *#* Fix Doxygen markup.
+ *#* Revision 1.27 2004/12/31 17:02:47 bernie
+ *#* IRQ_SAVE_DISABLE(), IRQ_RESTORE(): Add null stubs for x86.
*#*
- *#* Revision 1.18 2004/10/03 18:36:31 bernie
- *#* IRQ_GETSTATE(): New macro; Rename IRQ macros for consistency.
+ *#* Revision 1.26 2004/12/13 12:08:12 bernie
+ *#* DISABLE_IRQSAVE, ENABLE_IRQRESTORE, DISABLE_INTS, ENABLE_INTS: Remove obsolete macros.
*#*
- *#* Revision 1.17 2004/09/06 21:48:27 bernie
- *#* ATOMIC(): New macro.
- *#*
- *#* Revision 1.16 2004/08/29 21:58:33 bernie
- *#* Rename BITS_PER_XYZ macros; Add sanity checks.
- *#*
- *#* Revision 1.15 2004/08/25 14:12:08 rasky
- *#* Aggiornato il comment block dei log RCS
- *#*
- *#* Revision 1.14 2004/08/24 13:29:28 bernie
- *#* Trim CVS log; Rename header guards.
- *#*
- *#* Revision 1.12 2004/08/14 19:37:57 rasky
- *#* Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
- *#*
- *#* Revision 1.11 2004/08/05 17:39:56 bernie
- *#* Fix a Doxygen tag.
- *#*
- *#* Revision 1.10 2004/08/02 20:20:29 aleph
- *#* Merge from project_ks
- *#*
- *#* Revision 1.9 2004/07/30 14:24:16 rasky
- *#* Task switching con salvataggio perfetto stato di interrupt (SR)
- *#* Kernel monitor per dump informazioni su stack dei processi
+ *#* Revision 1.25 2004/12/08 08:31:02 bernie
+ *#* CPU_HARVARD: Define to 1 for AVR and DSP56K.
*#*/
#ifndef DEVLIB_CPU_H
#define DEVLIB_CPU_H
-#include "compiler.h" /* for uintXX_t, PP_CAT3(), PP_STRINGIZE() */
+#include "compiler.h" /* for uintXX_t */
/*!
#define NOP asm volatile ("nop")
#define IRQ_DISABLE /* nothing */
#define IRQ_ENABLE /* nothing */
+ #define IRQ_SAVE_DISABLE(x) /* nothing */
+ #define IRQ_RESTORE(x) /* nothing */
typedef uint32_t cpuflags_t; // FIXME
typedef uint32_t cpustack_t;
#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
#define CPU_HARVARD 0
+#elif CPU_PPC
+ #define NOP asm volatile ("nop" ::)
+ #define IRQ_DISABLE FIXME
+ #define IRQ_ENABLE FIXME
+ #define IRQ_SAVE_DISABLE(x) FIXME
+ #define IRQ_RESTORE(x) FIXME
+ #define IRQ_GETSTATE() FIXME
+
+ typedef uint32_t cpuflags_t; // FIXME
+ typedef uint32_t cpustack_t; // FIXME
+
+ /* Register counts include SREG too */
+ #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
+ #define CPU_REGS_CNT FIXME
+ #define CPU_SAVED_REGS_CNT FIXME
+ #define CPU_STACK_GROWS_UPWARD 0 //FIXME
+ #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
+ #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
+ #define CPU_HARVARD 0
+
#elif CPU_DSP56K
#define NOP asm(nop)
+ #define BREAKPOINT asm(debug)
#define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
#define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
#define IRQ_RESTORE(x) \
do { (void)x; asm(move x,SR); } while (0)
+ static inline bool irq_running(void)
+ {
+ extern void *user_sp;
+ return !!user_sp;
+ }
+ #define IRQ_RUNNING() irq_running()
+
+ static inline bool irq_getstate(void)
+ {
+ uint16_t x;
+ asm(move SR,x);
+ return !(x & 0x0200);
+ }
+ #define IRQ_GETSTATE() irq_getstate()
+
+
typedef uint16_t cpuflags_t;
typedef unsigned int cpustack_t;
#define CPU_STACK_GROWS_UPWARD 1
#define CPU_SP_ON_EMPTY_SLOT 0
#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+ #define CPU_HARVARD 1
/* Memory is word-addessed in the DSP56K */
#define CPU_BITS_PER_CHAR 16
#define CPU_STACK_GROWS_UPWARD 0
#define CPU_SP_ON_EMPTY_SLOT 1
#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+ #define CPU_HARVARD 1
/*!
* Initialization value for registers in stack frame.
#endif
-/* OBSOLETE NAMES */
-#define DISABLE_INTS IRQ_DISABLE
-#define ENABLE_INTS IRQ_ENABLE
-#define DISABLE_IRQSAVE(x) IRQ_SAVE_DISABLE(x)
-#define ENABLE_IRQRESTORE(x) IRQ_RESTORE(x)
-
/*!
* Execute \a CODE atomically with respect to interrupts.
*
- * \see ENABLE_IRQSAVE DISABLE_IRQRESTORE
+ * \see IRQ_SAVE_DISABLE IRQ_RESTORE
*/
#define ATOMIC(CODE) \
do { \
cpuflags_t __flags; \
- DISABLE_IRQSAVE(__flags); \
+ IRQ_SAVE_DISABLE(__flags); \
CODE; \
- ENABLE_IRQRESTORE(__flags); \
+ IRQ_RESTORE(__flags); \
} while (0)
/*!
- * \name Default type sizes
- *
- * \def SIZEOF_CHAR SIZEOF_SHORT SIZEOF_INT SIZEOF_LONG SIZEOF_PTR
- * \def CPU_BITS_PER_CHAR CPU_BITS_PER_SHORT CPU_BITS_PER_INT
- * \def CPU_BITS_PER_LONG CPU_BITS_PER_PTR
+ * \name Default type sizes.
*
* These defaults are reasonable for most 16/32bit machines.
* Some of these macros may be overridden by CPU-specific code above.
#endif /* !SIZEOF_INT */
#ifndef SIZEOF_LONG
-#define SIZEOF_LONG 4
+#if CPU_REG_BITS > 32
+ #define SIZEOF_LONG 8
+#else
+ #define SIZEOF_LONG 4
+#endif
#endif
#ifndef SIZEOF_PTR
#ifndef CPU_BITS_PER_PTR
#define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
#endif
+
+#ifndef BREAKPOINT
+#define BREAKPOINT /* nop */
+#endif
+
/*\}*/
/* Sanity checks for the above definitions */
/*!
- * \def SCHEDULER_IDLE
+ * \def CPU_IDLE
*
* \brief Invoked by the scheduler to stop the CPU when idle.
*