* \author Stefano Fedrigo <aleph@develer.com>
*/
-/*
- * $Log$
- * Revision 1.13 2004/08/24 13:16:00 bernie
- * Add type-size definitions for preprocessor.
- *
- * Revision 1.12 2004/08/14 19:37:57 rasky
- * Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
- *
- * Revision 1.11 2004/08/05 17:39:56 bernie
- * Fix a Doxygen tag.
- *
- * Revision 1.10 2004/08/02 20:20:29 aleph
- * Merge from project_ks
- *
- * Revision 1.9 2004/07/30 14:24:16 rasky
- * Task switching con salvataggio perfetto stato di interrupt (SR)
- * Kernel monitor per dump informazioni su stack dei processi
- *
- * Revision 1.8 2004/07/30 14:15:53 rasky
- * Nuovo supporto unificato per detect della CPU
- *
- * Revision 1.7 2004/07/20 23:26:48 bernie
- * Fix two errors introduced by previous commit.
- *
- * Revision 1.6 2004/07/20 23:12:16 bernie
- * Rationalize and document SCHEDULER_IDLE.
- *
- * Revision 1.5 2004/07/20 16:20:35 bernie
- * Move byte-order macros to mware/byteorder.h; Add missing author names.
- *
- * Revision 1.4 2004/07/20 16:06:04 bernie
- * Add macros to handle endianess issues.
- *
- * Revision 1.3 2004/07/18 21:49:51 bernie
- * Fixes for GCC 3.5.
- *
- * Revision 1.2 2004/06/03 11:27:09 bernie
- * Add dual-license information.
- *
- * Revision 1.1 2004/05/23 17:48:35 bernie
- * Add top-level files.
- *
- */
-#ifndef CPU_H
-#define CPU_H
+/*#*
+ *#* $Log$
+ *#* Revision 1.23 2004/11/16 22:41:58 bernie
+ *#* Support 64bit CPUs.
+ *#*
+ *#* Revision 1.22 2004/11/16 21:57:59 bernie
+ *#* CPU_IDLE: Rename from SCHEDULER_IDLE.
+ *#*
+ *#* Revision 1.21 2004/11/16 21:34:25 bernie
+ *#* Commonize obsolete names for IRQ macros; Doxygen fixes.
+ *#*
+ *#* Revision 1.20 2004/11/16 20:33:32 bernie
+ *#* CPU_HARVARD: New macro.
+ *#*
+ *#* Revision 1.19 2004/10/03 20:43:54 bernie
+ *#* Fix Doxygen markup.
+ *#*
+ *#* Revision 1.18 2004/10/03 18:36:31 bernie
+ *#* IRQ_GETSTATE(): New macro; Rename IRQ macros for consistency.
+ *#*
+ *#* Revision 1.17 2004/09/06 21:48:27 bernie
+ *#* ATOMIC(): New macro.
+ *#*
+ *#* Revision 1.16 2004/08/29 21:58:33 bernie
+ *#* Rename BITS_PER_XYZ macros; Add sanity checks.
+ *#*
+ *#* Revision 1.15 2004/08/25 14:12:08 rasky
+ *#* Aggiornato il comment block dei log RCS
+ *#*
+ *#* Revision 1.14 2004/08/24 13:29:28 bernie
+ *#* Trim CVS log; Rename header guards.
+ *#*
+ *#* Revision 1.12 2004/08/14 19:37:57 rasky
+ *#* Merge da SC: macros.h, pool.h, BIT_CHANGE, nome dei processi, etc.
+ *#*
+ *#* Revision 1.11 2004/08/05 17:39:56 bernie
+ *#* Fix a Doxygen tag.
+ *#*
+ *#* Revision 1.10 2004/08/02 20:20:29 aleph
+ *#* Merge from project_ks
+ *#*
+ *#* Revision 1.9 2004/07/30 14:24:16 rasky
+ *#* Task switching con salvataggio perfetto stato di interrupt (SR)
+ *#* Kernel monitor per dump informazioni su stack dei processi
+ *#*/
+#ifndef DEVLIB_CPU_H
+#define DEVLIB_CPU_H
+
+#include "compiler.h" /* for uintXX_t, PP_CAT3(), PP_STRINGIZE() */
-#include "compiler.h"
-
-// Macros for determining CPU endianness
+/*!
+ * \name Macros for determining CPU endianness.
+ * \{
+ */
#define CPU_BIG_ENDIAN 0x1234
#define CPU_LITTLE_ENDIAN 0x3412
+/*\}*/
-// Macros to include cpu-specific version of the headers
+/*! Macro to include cpu-specific versions of the headers. */
#define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
#if CPU_I196
- #define DISABLE_INTS disable_interrupt()
- #define ENABLE_INTS enable_interrupt()
#define NOP nop_instruction()
+ #define IRQ_DISABLE disable_interrupt()
+ #define IRQ_ENABLE enable_interrupt()
typedef uint16_t cpuflags_t; // FIXME
typedef unsigned int cpustack_t;
#define CPU_STACK_GROWS_UPWARD 0
#define CPU_SP_ON_EMPTY_SLOT 0
#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+ #define CPU_HARVARD 0
#elif CPU_X86
#define NOP asm volatile ("nop")
- #define DISABLE_INTS /* nothing */
- #define ENABLE_INTS /* nothing */
+ #define IRQ_DISABLE /* nothing */
+ #define IRQ_ENABLE /* nothing */
typedef uint32_t cpuflags_t; // FIXME
typedef uint32_t cpustack_t;
#define CPU_STACK_GROWS_UPWARD 0
#define CPU_SP_ON_EMPTY_SLOT 0
#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+ #define CPU_HARVARD 0
#elif CPU_DSP56K
#define NOP asm(nop)
- #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0)
- #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
+ #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0)
+ #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
- #define DISABLE_IRQSAVE(x) \
+ #define IRQ_SAVE_DISABLE(x) \
do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0)
- #define ENABLE_IRQRESTORE(x) \
+ #define IRQ_RESTORE(x) \
do { (void)x; asm(move x,SR); } while (0)
+
typedef uint16_t cpuflags_t;
typedef unsigned int cpustack_t;
#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
/* Memory is word-addessed in the DSP56K */
- #define BITSP_PER_CHAR 16
- #define SIZEOF_SHORT 1
- #define SIZEOF_INT 1
- #define SIZEOF_LONG 2
- #define SIZEOF_PTR 1
+ #define CPU_BITS_PER_CHAR 16
+ #define SIZEOF_SHORT 1
+ #define SIZEOF_INT 1
+ #define SIZEOF_LONG 2
+ #define SIZEOF_PTR 1
#elif CPU_AVR
- #define NOP asm volatile ("nop" ::)
- #define DISABLE_INTS asm volatile ("cli" ::)
- #define ENABLE_INTS asm volatile ("sei" ::)
+ #define NOP asm volatile ("nop" ::)
+ #define IRQ_DISABLE asm volatile ("cli" ::)
+ #define IRQ_ENABLE asm volatile ("sei" ::)
- #define DISABLE_IRQSAVE(x) \
+ #define IRQ_SAVE_DISABLE(x) \
do { \
__asm__ __volatile__( \
"in %0,__SREG__\n\t" \
); \
} while (0)
- #define ENABLE_IRQRESTORE(x) \
+ #define IRQ_RESTORE(x) \
do { \
__asm__ __volatile__( \
"out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \
); \
} while (0)
+ #define IRQ_GETSTATE() \
+ ({ \
+ uint8_t sreg; \
+ __asm__ __volatile__( \
+ "in %0,__SREG__\n\t" \
+ : "=r" (sreg) /* no inputs & no clobbers */ \
+ ); \
+ (bool)(sreg & 0x80); \
+ })
+
typedef uint8_t cpuflags_t;
typedef uint8_t cpustack_t;
#endif
+/* OBSOLETE NAMES */
+#define DISABLE_INTS IRQ_DISABLE
+#define ENABLE_INTS IRQ_ENABLE
+#define DISABLE_IRQSAVE(x) IRQ_SAVE_DISABLE(x)
+#define ENABLE_IRQRESTORE(x) IRQ_RESTORE(x)
+
+/*!
+ * Execute \a CODE atomically with respect to interrupts.
+ *
+ * \see ENABLE_IRQSAVE DISABLE_IRQRESTORE
+ */
+#define ATOMIC(CODE) \
+ do { \
+ cpuflags_t __flags; \
+ DISABLE_IRQSAVE(__flags); \
+ CODE; \
+ ENABLE_IRQRESTORE(__flags); \
+ } while (0)
+
//! Default for macro not defined in the right arch section
#ifndef CPU_REG_INIT_VALUE
#if CPU_DSP56K
- /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
+ /*
+ * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
* RTS discards SR while returning (it does not restore it). So we push
* 0 to fake the same context.
*/
} while (0);
#elif CPU_AVR
- /* In AVR, the addresses are pushed into the stack as little-endian, while
+ /*
+ * In AVR, the addresses are pushed into the stack as little-endian, while
* memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
* no natural endianess).
*/
/*!
- * \def SIZEOF_CHAR SIZEOF_SHORT SIZEOF_INT SIZEOF_LONG SIZEOF_PTR
- * \def BITS_PER_CHAR BITS_PER_SHORT BITS_PER_INT BITS_PER_LONG BITS_PER_PTR
+ * \name Default type sizes
*
- * \brief Default type sizes
+ * \def SIZEOF_CHAR SIZEOF_SHORT SIZEOF_INT SIZEOF_LONG SIZEOF_PTR
+ * \def CPU_BITS_PER_CHAR CPU_BITS_PER_SHORT CPU_BITS_PER_INT
+ * \def CPU_BITS_PER_LONG CPU_BITS_PER_PTR
*
* These defaults are reasonable for most 16/32bit machines.
* Some of these macros may be overridden by CPU-specific code above.
*
- * ANSI C specifies that the following equations must be true:
+ * ANSI C requires that the following equations be true:
* \code
* sizeof(char) <= sizeof(short) <= sizeof(int) <= sizeof(long)
* sizeof(float) <= sizeof(double)
- * BITS_PER_CHAR >= 8
- * BITS_PER_SHORT >= 8
- * BITS_PER_INT >= 16
- * BITS_PER_LONG >= 32
- * \end code
+ * CPU_BITS_PER_CHAR >= 8
+ * CPU_BITS_PER_SHORT >= 8
+ * CPU_BITS_PER_INT >= 16
+ * CPU_BITS_PER_LONG >= 32
+ * \endcode
* \{
*/
#ifndef SIZEOF_CHAR
#endif /* !SIZEOF_INT */
#ifndef SIZEOF_LONG
-#define SIZEOF_LONG 4
+#if CPU_REG_BITS > 32
+ #define SIZEOF_LONG 8
+#else
+ #define SIZEOF_LONG 4
+#endif
#endif
#ifndef SIZEOF_PTR
#define SIZEOF_PTR SIZEOF_INT
#endif
-#ifndef BITS_PER_CHAR
-#define BITS_PER_CHAR (SIZEOF_CHAR * 8)
+#ifndef CPU_BITS_PER_CHAR
+#define CPU_BITS_PER_CHAR (SIZEOF_CHAR * 8)
#endif
-#ifndef BITS_PER_SHORT
-#define BITS_PER_SHORT (SIZEOF_SHORT * BITS_PER_CHAR)
+#ifndef CPU_BITS_PER_SHORT
+#define CPU_BITS_PER_SHORT (SIZEOF_SHORT * CPU_BITS_PER_CHAR)
#endif
-#ifndef BITS_PER_INT
-#define BITS_PER_INT (SIZEOF_INT * BITS_PER_CHAR)
+#ifndef CPU_BITS_PER_INT
+#define CPU_BITS_PER_INT (SIZEOF_INT * CPU_BITS_PER_CHAR)
#endif
-#ifndef BITS_PER_LONG
-#define BITS_PER_LONG (SIZEOF_LONG * BITS_PER_CHAR)
+#ifndef CPU_BITS_PER_LONG
+#define CPU_BITS_PER_LONG (SIZEOF_LONG * CPU_BITS_PER_CHAR)
#endif
-#ifndef BITS_PER_PTR
-#define BITS_PER_PTR (SIZEOF_PTR * BITS_PER_CHAR)
+#ifndef CPU_BITS_PER_PTR
+#define CPU_BITS_PER_PTR (SIZEOF_PTR * CPU_BITS_PER_CHAR)
#endif
/*\}*/
+/* Sanity checks for the above definitions */
+STATIC_ASSERT(sizeof(char) == SIZEOF_CHAR);
+STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
+STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
+STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
+
/*!
* \def SCHEDULER_IDLE
* profile system load with an external strobe, or to save CPU cycles
* in hosted environments such as emulators.
*/
-#ifndef SCHEDULER_IDLE
+#ifndef CPU_IDLE
#if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
/* This emulator hook should yield the CPU to the host. */
EXTERN_C_BEGIN
void SchedulerIdle(void);
EXTERN_C_END
- #define SCHEDULER_IDLE SchedulerIdle()
+ #define CPU_IDLE SchedulerIdle()
#else /* !ARCH_EMUL */
- #define SCHEDULER_IDLE do { /* nothing */ } while (0)
+ #define CPU_IDLE do { /* nothing */ } while (0)
#endif /* !ARCH_EMUL */
-#endif /* !SCHEDULER_IDLE */
+#endif /* !CPU_IDLE */
+
+/* OBSOLETE */
+#define SCHEDULER_IDLE CPU_IDLE
-#endif /* CPU_H */
+#endif /* DEVLIB_CPU_H */
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