Adjust for DevLib.

[bertos.git] / cpu.h

diff --git a/cpu.h b/cpu.h
index 4715908b3d5666804b1a7209fb8f2f7a1ffdb41e..9b77378e139b1b7af2bb0e1616a771eea33e7781 100755 (executable)
--- a/cpu.h
+++ b/cpu.h
@@ -17,6 +17,19 @@
 
 /*
  * $Log$
+ * Revision 1.11  2004/08/05 17:39:56  bernie
+ * Fix a Doxygen tag.
+ *
+ * Revision 1.10  2004/08/02 20:20:29  aleph
+ * Merge from project_ks
+ *
+ * Revision 1.9  2004/07/30 14:24:16  rasky
+ * Task switching con salvataggio perfetto stato di interrupt (SR)
+ * Kernel monitor per dump informazioni su stack dei processi
+ *
+ * Revision 1.8  2004/07/30 14:15:53  rasky
+ * Nuovo supporto unificato per detect della CPU
+ *
  * Revision 1.7  2004/07/20 23:26:48  bernie
  * Fix two errors introduced by previous commit.
  *
@@ -44,15 +57,16 @@
 
 #include "compiler.h"
 
-//! Initialization value for registers in stack frame
-#define CPU_REG_INIT_VALUE(reg)     0
 
 // Macros for determining CPU endianness
 #define CPU_BIG_ENDIAN    0x1234
 #define CPU_LITTLE_ENDIAN 0x3412
 
+// Macros to include cpu-specific version of the headers
+#define CPU_HEADER(module)          PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
+
 
-#if defined(__IAR_SYSTEMS_ICC) || defined(__IAR_SYSTEMS_ICC__)  /* 80C196 */
+#if CPU_I196
 
        #define DISABLE_INTS            disable_interrupt()
        #define ENABLE_INTS             enable_interrupt()
@@ -66,7 +80,7 @@
        #define CPU_SP_ON_EMPTY_SLOT    0
        #define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
 
-#elif defined(__i386__) || defined(_MSC_VER) /* x86 */
+#elif CPU_X86
 
        #define NOP                     asm volatile ("nop")
        #define DISABLE_INTS            /* nothing */
@@ -80,7 +94,7 @@
        #define CPU_SP_ON_EMPTY_SLOT    0
        #define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
 
-#elif defined(__m56800E__) || defined(__m56800__) /* DSP56K */
+#elif CPU_DSP56K
 
        #define NOP                     asm(nop)
        #define DISABLE_INTS            do { asm(bfset #0x0200,SR); asm(nop); } while (0)
@@ -95,26 +109,12 @@
        typedef unsigned int cpustack_t;
 
        #define CPU_REGS_CNT            FIXME
-       #define CPU_SAVED_REGS_CNT      28
+       #define CPU_SAVED_REGS_CNT      8
        #define CPU_STACK_GROWS_UPWARD  1
        #define CPU_SP_ON_EMPTY_SLOT    0
        #define CPU_BYTE_ORDER          CPU_BIG_ENDIAN
 
-       #undef CPU_REG_INIT_VALUE
-       INLINE uint16_t CPU_REG_INIT_VALUE(int reg)
-       {
-               if (reg == 14)
-               {
-                       uint16_t omr_img;
-                       asm(move OMR, omr_img);
-                       return omr_img & (BV(3)/*EX*/ | BV(1)/*MB*/ | BV(0)/*MA*/);
-               }
-               else if (reg == 16)/*M01*/
-                       return 0xFFFF;
-               return 0;
-       }
-
-#elif defined (__AVR__)
+#elif CPU_AVR
 
        #define NOP                     asm volatile ("nop" ::)
        #define DISABLE_INTS            asm volatile ("cli" ::)
@@ -139,13 +139,27 @@
        typedef uint8_t cpuflags_t;
        typedef uint8_t cpustack_t;
 
-       #define CPU_REGS_CNT            32
-       #define CPU_SAVED_REGS_CNT      18
+       /* Register counts include SREG too */
+       #define CPU_REGS_CNT            33
+       #define CPU_SAVED_REGS_CNT      19
        #define CPU_STACK_GROWS_UPWARD  0
        #define CPU_SP_ON_EMPTY_SLOT    1
        #define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
-#else
-       #error Unknown CPU
+
+       /*!
+        * Initialization value for registers in stack frame.
+        * The register index is not directly corrispondent to CPU
+        * register numbers. Index 0 is the SREG register: the initial
+        * value is all 0 but the interrupt bit (bit 7).
+        */
+       #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
+
+#endif
+
+
+//! Default for macro not defined in the right arch section
+#ifndef CPU_REG_INIT_VALUE
+       #define CPU_REG_INIT_VALUE(reg)     0
 #endif
 
 
@@ -192,7 +206,7 @@
 #endif
 
 
-#if defined(__m56800E__) || defined(__m56800__)
+#if CPU_DSP56K
        /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but
         * RTS discards SR while returning (it does not restore it). So we push
         * 0 to fake the same context.
@@ -200,10 +214,10 @@
        #define CPU_PUSH_CALL_CONTEXT(sp, func) \
                do { \
                        CPU_PUSH_WORD((sp), (func)); \
-                       CPU_PUSH_WORD((sp), 0); \
+                       CPU_PUSH_WORD((sp), 0x100); \
                } while (0);
 
-#elif defined (__AVR__)
+#elif CPU_AVR
        /* In AVR, the addresses are pushed into the stack as little-endian, while
         * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
         * no natural endianess).
@@ -222,7 +236,7 @@
 
 
 /*!
- * \name SCHEDULER_IDLE
+ * \def SCHEDULER_IDLE
  *
  * \brief Invoked by the scheduler to stop the CPU when idle.
  *