/*#*
*#* $Log$
+ *#* Revision 1.34 2006/11/23 13:19:02 batt
+ *#* Add support for ATmega1281.
+ *#*
+ *#* Revision 1.33 2006/09/13 18:21:24 bernie
+ *#* Add configurable SPI pin mapping.
+ *#*
*#* Revision 1.32 2006/07/19 12:56:26 bernie
*#* Convert to new Doxygen style.
*#*
#include "ser.h"
#include "ser_p.h"
-#include "hw_ser.h" /* Required for bus macros overrides */
+
+#include <hw_ser.h> /* Required for bus macros overrides */
+#include <hw_cpu.h> /* CLOCK_FREQ */
#include <appconfig.h>
#include <cfg/debug.h>
/*\}*/
#endif
+#if CPU_AVR_ATMEGA1281
+ #define BIT_RXCIE0 RXCIE0
+ #define BIT_RXEN0 RXEN0
+ #define BIT_TXEN0 TXEN0
+ #define BIT_UDRIE0 UDRIE0
+
+ #define BIT_RXCIE1 RXCIE1
+ #define BIT_RXEN1 RXEN1
+ #define BIT_TXEN1 TXEN1
+ #define BIT_UDRIE1 UDRIE1
+#else
+ #define BIT_RXCIE0 RXCIE
+ #define BIT_RXEN0 RXEN
+ #define BIT_TXEN0 TXEN
+ #define BIT_UDRIE0 UDRIE
+
+ #define BIT_RXCIE1 RXCIE
+ #define BIT_RXEN1 RXEN
+ #define BIT_TXEN1 TXEN
+ #define BIT_UDRIE1 UDRIE
+#endif
+
/**
* \name Overridable serial bus hooks
* - Enable only the RX complete interrupt
*/
#define SER_UART0_BUS_TXINIT do { \
- UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
+ UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
} while (0)
#endif
* - Enable both the RX complete and UDR empty interrupts
*/
#define SER_UART0_BUS_TXBEGIN do { \
- UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
+ UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
} while (0)
#endif
* - Disable the UDR empty interrupt
*/
#define SER_UART0_BUS_TXEND do { \
- UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
+ UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
} while (0)
#endif
#ifndef SER_UART1_BUS_TXINIT
/** \sa SER_UART0_BUS_TXINIT */
#define SER_UART1_BUS_TXINIT do { \
- UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
+ UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
} while (0)
#endif
#ifndef SER_UART1_BUS_TXBEGIN
/** \sa SER_UART0_BUS_TXBEGIN */
#define SER_UART1_BUS_TXBEGIN do { \
- UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
+ UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
} while (0)
#endif
#ifndef SER_UART1_BUS_TXCHAR
#ifndef SER_UART1_BUS_TXEND
/** \sa SER_UART0_BUS_TXEND */
#define SER_UART1_BUS_TXEND do { \
- UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
+ UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
} while (0)
#endif
#ifndef SER_UART1_BUS_TXOFF
/* SPI port and pin configuration */
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
+#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281
#define SPI_PORT PORTB
#define SPI_DDR DDRB
+ #define SPI_SS_BIT PB0
#define SPI_SCK_BIT PB1
#define SPI_MOSI_BIT PB2
#define SPI_MISO_BIT PB3
#elif CPU_AVR_ATMEGA8
#define SPI_PORT PORTB
#define SPI_DDR DDRB
+ #define SPI_SS_BIT PB2
#define SPI_SCK_BIT PB5
#define SPI_MOSI_BIT PB3
#define SPI_MISO_BIT PB4
#endif
/* USART register definitions */
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
+#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
#define AVR_HAS_UART1 1
#elif CPU_AVR_ATMEGA8
#define AVR_HAS_UART1 0
static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
{
#if !CPU_AVR_ATMEGA103
- UCSR0C = (UCSR0C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
+ UCSR0C = (UCSR0C & ~(BV(UPM01) | BV(UPM00))) | ((parity) << UPM00);
#endif
}
static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
{
- UCSR1C = (UCSR1C & ~(BV(UPM1) | BV(UPM0))) | ((parity) << UPM0);
+ UCSR1C = (UCSR1C & ~(BV(UPM11) | BV(UPM10))) | ((parity) << UPM10);
}
#endif // AVR_HAS_UART1
* with the KBus serial RX, and the transmitter of the slave boards
* would be unable to drive the line.
*/
- SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
- SPI_DDR &= ~BV(SPI_MISO_BIT);
- /* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
- SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
+ ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
+
+ /*
+ * If the SPI master mode is activated and the SS pin is in input and tied low,
+ * the SPI hardware will automatically switch to slave mode!
+ * For proper communication this pins should therefore be:
+ * - as output
+ * - as input but tied high forever!
+ * This driver set the pin as output.
+ */
+ #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts.
+ ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
+ ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
+ /* Enable SPI, IRQ on, Master */
+ SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
+
+ /* Set data order */
+ #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
+ SPCR |= BV(DORD);
+ #endif
+
+ /* Set SPI clock rate */
+ #if CONFIG_SPI_CLOCK_DIV == 128
+ SPCR |= (BV(SPR1) | BV(SPR0));
+ #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
+ SPCR |= BV(SPR1);
+ #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
+ SPCR |= BV(SPR0);
+ #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
+ // SPR0 & SDPR1 both at 0
+ #else
+ #error Unsupported SPI clock division factor.
+ #endif
+
+ /* Set SPI2X bit (spi double frequency) */
+ #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
+ || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
+ SPSR &= ~BV(SPI2X);
+ #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
+ SPSR |= BV(SPI2X);
+ #else
+ #error Unsupported SPI clock division factor.
+ #endif
+
+ /* Set clock polarity */
+ #if CONFIG_SPI_CLOCK_POL == 1
+ SPCR |= BV(CPOL);
+ #endif
+
+ /* Set clock phase */
+ #if CONFIG_SPI_CLOCK_PHASE == 1
+ SPCR |= BV(CPHA);
+ #endif
SER_SPI_BUS_TXINIT;
SER_STROBE_INIT;
SER_SPI_BUS_TXCLOSE;
/* Set all pins as inputs */
- SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
+ ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
}
static void spi_starttx(struct SerialHardware *_hw)
/**
* Serial 0 TX interrupt handler
*/
-SIGNAL(SIG_UART0_DATA)
+SIGNAL(USART0_UDRE_vect)
{
SER_STROBE_ON;
/**
* Serial 1 TX interrupt handler
*/
-SIGNAL(SIG_UART1_DATA)
+SIGNAL(USART1_UDRE_vect)
{
SER_STROBE_ON;
* RXCIE is cleared. Unfortunately the RXC flag is read-only
* and can't be cleared by code.
*/
-SIGNAL(SIG_UART0_RECV)
+SIGNAL(USART0_RX_vect)
{
SER_STROBE_ON;
* is heavily loaded, because an interrupt could be retriggered
* when executing the handler prologue before RXCIE is disabled.
*
- * \see SIGNAL(SIG_UART0_RECV)
+ * \see SIGNAL(USART1_RX_vect)
*/
-SIGNAL(SIG_UART1_RECV)
+SIGNAL(USART1_RX_vect)
{
SER_STROBE_ON;
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