* <!--
* Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
* Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
- * This file is part of DevLib - See devlib/README for information.
+ * This file is part of DevLib - See README.devlib for information.
* -->
*
* \brief AVR UART and SPI I/O driver
/*#*
*#* $Log$
+ *#* Revision 1.31 2006/05/18 00:37:29 bernie
+ *#* Use hw_ser.h instead of ubiquitous hw.h.
+ *#*
+ *#* Revision 1.30 2006/02/17 22:23:06 bernie
+ *#* Update POSIX serial emulator.
+ *#*
+ *#* Revision 1.29 2005/11/27 23:31:48 bernie
+ *#* Support avr-libc 1.4.
+ *#*
+ *#* Revision 1.28 2005/11/04 16:20:02 bernie
+ *#* Fix reference to README.devlib in header.
+ *#*
+ *#* Revision 1.27 2005/07/03 15:19:31 bernie
+ *#* Doxygen fix.
+ *#*
+ *#* Revision 1.26 2005/04/11 19:10:27 bernie
+ *#* Include top-level headers from cfg/ subdir.
+ *#*
+ *#* Revision 1.25 2005/01/25 08:37:26 bernie
+ *#* CONFIG_SER_HWHANDSHAKE fixes.
+ *#*
+ *#* Revision 1.24 2005/01/14 00:49:16 aleph
+ *#* Rename callbacks; SerialHardwareVT.txSending: New callback; Add SPI_BUS macros.
+ *#*
+ *#* Revision 1.23 2005/01/11 18:09:07 aleph
+ *#* Add ATmega8 SPI port definitions; Fix transmit complete IRQ bug; add strobe macros to uart1 and spi
+ *#*
*#* Revision 1.22 2004/12/31 17:47:45 bernie
*#* Rename UNUSED() to UNUSED_ARG().
*#*
#include "ser.h"
#include "ser_p.h"
-#include "config.h"
-#include "hw.h" /* Required for bus macros overrides */
+#include "hw_ser.h" /* Required for bus macros overrides */
+#include <appconfig.h>
-#include <debug.h>
+#include <cfg/debug.h>
#include <drv/timer.h>
#include <mware/fifobuf.h>
-#include <avr/signal.h>
#include <avr/io.h>
+#if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL)
+ #include <avr/interrupt.h>
+#else
+ #include <avr/signal.h>
+#endif
-/*!
- * \name Hardware handshake (RTS/CTS).
- * \{
- */
-#ifndef RTS_ON
-#define RTS_ON do {} while (0)
-#endif
-#ifndef RTS_OFF
-#define RTS_OFF do {} while (0)
-#endif
-#ifndef IS_CTS_ON
-#define IS_CTS_ON true
-#endif
-#ifndef EIMSKB_CTS
-#define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
+#if !CONFIG_SER_HWHANDSHAKE
+ /*!
+ * \name Hardware handshake (RTS/CTS).
+ * \{
+ */
+ #define RTS_ON do {} while (0)
+ #define RTS_OFF do {} while (0)
+ #define IS_CTS_ON true
+ #define EIMSKF_CTS 0 /*!< Dummy value, must be overridden */
+ /*\}*/
#endif
-/*\}*/
/*!
/*\}*/
+/*!
+ * \name Overridable SPI hooks
+ *
+ * These can be redefined in hw.h to implement
+ * special bus policies such as slave select pin handling, etc.
+ *
+ * \{
+ */
+#ifndef SER_SPI_BUS_TXINIT
+ /*!
+ * Default TXINIT macro - invoked in spi_init()
+ * The default is no action.
+ */
+ #define SER_SPI_BUS_TXINIT
+#endif
+
+#ifndef SER_SPI_BUS_TXCLOSE
+ /*!
+ * Invoked after the last character has been transmitted.
+ * The default is no action.
+ */
+ #define SER_SPI_BUS_TXCLOSE
+#endif
+/*\}*/
+
+
/* SPI port and pin configuration */
-#define SPI_PORT PORTB
-#define SPI_DDR DDRB
-#define SPI_SCK_BIT PB1
-#define SPI_MOSI_BIT PB2
-#define SPI_MISO_BIT PB3
+#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
+ #define SPI_PORT PORTB
+ #define SPI_DDR DDRB
+ #define SPI_SCK_BIT PB1
+ #define SPI_MOSI_BIT PB2
+ #define SPI_MISO_BIT PB3
+#elif CPU_AVR_ATMEGA8
+ #define SPI_PORT PORTB
+ #define SPI_DDR DDRB
+ #define SPI_SCK_BIT PB5
+ #define SPI_MOSI_BIT PB3
+ #define SPI_MISO_BIT PB4
+#else
+ #error Unknown architecture
+#endif
/* USART register definitions */
#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
#define UBRR0H UBRRH
#define SIG_UART0_DATA SIG_UART_DATA
#define SIG_UART0_RECV SIG_UART_RECV
+ #define SIG_UART0_TRANS SIG_UART_TRANS
#elif CPU_AVR_ATMEGA103
#define AVR_HAS_UART1 0
#define UCSR0B UCR
#define UBRR0L UBRR
#define SIG_UART0_DATA SIG_UART_DATA
#define SIG_UART0_RECV SIG_UART_RECV
+ #define SIG_UART0_TRANS SIG_UART_TRANS
#else
#error Unknown architecture
#endif
{
SER_UART0_BUS_TXINIT;
RTS_ON;
+ SER_STROBE_INIT;
}
static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
/* Compute baud-rate period */
uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
-#ifndef __AVR_ATmega103__
+#if !CPU_AVR_ATMEGA103
UBRR0H = (period) >> 8;
#endif
UBRR0L = (period);
SPI_DDR &= ~BV(SPI_MISO_BIT);
/* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
+
+ SER_SPI_BUS_TXINIT;
+
+ SER_STROBE_INIT;
}
static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
{
SPCR = 0;
+
+ SER_SPI_BUS_TXCLOSE;
+
/* Set all pins as inputs */
SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
}
// nop
}
+static bool tx_sending(struct SerialHardware* _hw)
+{
+ struct AvrSerial *hw = (struct AvrSerial *)_hw;
+ return hw->sending;
+}
+
+
// FIXME: move into compiler.h? Ditch?
#if COMPILER_C99
{
C99INIT(init, uart0_init),
C99INIT(cleanup, uart0_cleanup),
- C99INIT(setbaudrate, uart0_setbaudrate),
- C99INIT(setparity, uart0_setparity),
- C99INIT(enabletxirq, uart0_enabletxirq),
+ C99INIT(setBaudrate, uart0_setbaudrate),
+ C99INIT(setParity, uart0_setparity),
+ C99INIT(txStart, uart0_enabletxirq),
+ C99INIT(txSending, tx_sending),
};
#if AVR_HAS_UART1
{
C99INIT(init, uart1_init),
C99INIT(cleanup, uart1_cleanup),
- C99INIT(setbaudrate, uart1_setbaudrate),
- C99INIT(setparity, uart1_setparity),
- C99INIT(enabletxirq, uart1_enabletxirq),
+ C99INIT(setBaudrate, uart1_setbaudrate),
+ C99INIT(setParity, uart1_setparity),
+ C99INIT(txStart, uart1_enabletxirq),
+ C99INIT(txSending, tx_sending),
};
#endif // AVR_HAS_UART1
{
C99INIT(init, spi_init),
C99INIT(cleanup, spi_cleanup),
- C99INIT(setbaudrate, spi_setbaudrate),
- C99INIT(setparity, spi_setparity),
- C99INIT(enabletxirq, spi_starttx),
+ C99INIT(setBaudrate, spi_setbaudrate),
+ C99INIT(setParity, spi_setparity),
+ C99INIT(txStart, spi_starttx),
+ C99INIT(txSending, tx_sending),
};
static struct AvrSerial UARTDescs[SER_CNT] =
}
};
-struct SerialHardware* ser_hw_getdesc(int unit)
+struct SerialHardware *ser_hw_getdesc(int unit)
{
ASSERT(unit < SER_CNT);
return &UARTDescs[unit].hw;
{
// Re-enable UDR empty interrupt and TX, then disable CTS interrupt
UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
- cbi(EIMSK, EIMSKB_CTS);
+ EIMSK &= ~EIMSKF_CTS;
}
#endif // CONFIG_SER_HWHANDSHAKE
// Disable rx interrupt and tx, enable CTS interrupt
// UNTESTED
UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
- sbi(EIFR, EIMSKB_CTS);
- sbi(EIMSK, EIMSKB_CTS);
+ EIFR |= EIMSKF_CTS;
+ EIMSK |= EIMSKF_CTS;
}
#endif
else
// Disable rx interrupt and tx, enable CTS interrupt
// UNTESTED
UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
- sbi(EIFR, EIMSKB_CTS);
- sbi(EIMSK, EIMSKB_CTS);
+ EIFR |= EIMSKF_CTS;
+ EIMSK |= EIMSKF_CTS;
}
#endif
else
*/
SIGNAL(SIG_SPI)
{
+ SER_STROBE_ON;
+
/* Read incoming byte. */
if (!fifo_isfull(&ser_spi->rxfifo))
fifo_push(&ser_spi->rxfifo, SPDR);
SPDR = fifo_pop(&ser_spi->txfifo);
else
UARTDescs[SER_SPI].sending = false;
+
+ SER_STROBE_OFF;
}
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