/*!
* \file
* <!--
+ * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
* Copyright 2000 Bernardo Innocenti <bernie@codewiz.org>
- * Copyright 2003,2004 Develer S.r.l. (http://www.develer.com/)
* This file is part of DevLib - See devlib/README for information.
* -->
*
*
* \version $Id$
* \author Bernardo Innocenti <bernie@develer.com>
+ * \author Stefano Fedrigo <aleph@develer.com>
*/
/*
* $Log$
+ * Revision 1.10 2004/08/10 06:30:41 bernie
+ * Major redesign of serial bus policy handling.
+ *
+ * Revision 1.9 2004/08/02 20:20:29 aleph
+ * Merge from project_ks
+ *
+ * Revision 1.8 2004/07/29 22:57:09 bernie
+ * Several tweaks to reduce code size on ATmega8.
+ *
* Revision 1.7 2004/07/18 21:54:23 bernie
* Add ATmega8 support.
*
#include "kdebug.h"
#include "config.h"
#include "hw.h"
+#include <drv/timer.h>
#include <mware/fifobuf.h>
#include <avr/signal.h>
-extern struct Serial ser_handles[SER_CNT];
+/*!
+ * \name Hardware handshake (RTS/CTS).
+ * \{
+ */
+#ifndef RTS_ON
+#define RTS_ON do {} while (0)
+#endif
+#ifndef RTS_OFF
+#define RTS_OFF do {} while (0)
+#endif
+#ifndef IS_CTS_ON
+#define IS_CTS_ON true
+#endif
+#ifndef EIMSKB_CTS
+#define EIMSKB_CTS 0 /*!< Dummy value, must be overridden */
+#endif
+/*\}*/
-struct AvrSerial
-{
- struct SerialHardware hw;
- struct Serial* serial;
-};
+
+/*!
+ * \def CONFIG_SER_STROBE
+ *
+ * This is a debug facility that can be used to
+ * monitor SER interrupt activity on an external pin.
+ *
+ * To use strobes, redefine the macros SER_STROBE_ON,
+ * SER_STROBE_OFF and SER_STROBE_INIT and set
+ * CONFIG_SER_STROBE to 1.
+ */
+#ifndef CONFIG_SER_STROBE
+ #define SER_STROBE_ON do {/*nop*/} while(0)
+ #define SER_STROBE_OFF do {/*nop*/} while(0)
+ #define SER_STROBE_INIT do {/*nop*/} while(0)
+#endif
-/* Hardware handshake */
-#define RTS_ON
-#define RTS_OFF
-#define IS_CTS_ON true
-#define IS_CTS_OFF false
+/*!
+ * \name Overridable serial hooks
+ *
+ * These can be redefined in hw.h to implement
+ * special bus policies such as half-duplex, 485, etc.
+ *
+ *
+ * \code
+ * TXBEGIN TXCHAR TXEND TXOFF
+ * | __________|__________ | |
+ * | | | | | | | | |
+ * v v v v v v v v v
+ * ______ __ __ __ __ __ __ ________________
+ * \/ \/ \/ \/ \/ \/ \/
+ * ______/\__/\__/\__/\__/\__/\__/
+ *
+ * \endcode
+ *
+ * \{
+ */
+#ifndef SER_UART0_BUS_TXINIT
+ /*!
+ * Default TXINIT macro - invoked in uart0_init()
+ *
+ * - Enable both the receiver and the transmitter
+ * - Enable only the RX complete interrupt
+ */
+ #define SER_UART0_BUS_TXINIT do { \
+ UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXBEGIN
+ /*!
+ * Invoked before starting a transmission
+ *
+ * - Enable both the receiver and the transmitter
+ * - Enable both the RX complete and UDR empty interrupts
+ */
+ #define SER_UART0_BUS_TXBEGIN do { \
+ UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXCHAR
+ /*!
+ * Invoked to send one character.
+ */
+ #define SER_UART0_BUS_TXCHAR(c) do { \
+ UDR0 = (c); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXEND
+ /*!
+ * Invoked as soon as the txfifo becomes empty
+ *
+ * - Keep both the receiver and the transmitter enabled
+ * - Keep the RX complete interrupt enabled
+ * - Disable the UDR empty interrupt
+ */
+ #define SER_UART0_BUS_TXEND do { \
+ UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
+ } while (0)
+#endif
+
+#ifndef SER_UART0_BUS_TXOFF
+ /*!
+ * \def SER_UART0_BUS_TXOFF
+ *
+ * Invoked after the last character has been transmitted
+ *
+ * The default is no action.
+ */
+#endif
+
+#ifndef SER_UART1_BUS_TXINIT
+ /*! \sa SER_UART0_BUS_TXINIT */
+ #define SER_UART1_BUS_TXINIT do { \
+ UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
+ } while (0)
+#endif
+#ifndef SER_UART1_BUS_TXBEGIN
+ /*! \sa SER_UART0_BUS_TXBEGIN */
+ #define SER_UART1_BUS_TXBEGIN do { \
+ UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
+ } while (0)
+#endif
+#ifndef SER_UART1_BUS_TXCHAR
+ /*! \sa SER_UART0_BUS_TXCHAR */
+ #define SER_UART1_BUS_TXCHAR(c) do { \
+ UDR1 = (c); \
+ } while (0)
+#endif
+#ifndef SER_UART1_BUS_TXEND
+ /*! \sa SER_UART0_BUS_TXEND */
+ #define SER_UART1_BUS_TXEND do { \
+ UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
+ } while (0)
+#endif
+#ifndef SER_UART1_BUS_TXOFF
+ /*!
+ * \def SER_UART1_BUS_TXOFF
+ *
+ * \see SER_UART0_BUS_TXOFF
+ */
+#endif
+/*\}*/
/* SPI port and pin configuration */
#define SPI_MOSI_BIT PORTB2
#define SPI_MISO_BIT PORTB3
-
+/* USART registers definitions */
#if defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__)
- #define AVR_HAS_UART1
+ #define AVR_HAS_UART1 1
#elif defined(__AVR_ATmega8__)
+ #define AVR_HAS_UART1 0
#define UCSR0A UCSRA
#define UCSR0B UCSRB
#define UCSR0C UCSRC
#define SIG_UART0_DATA SIG_UART_DATA
#define SIG_UART0_RECV SIG_UART_RECV
#elif defined(__AVR_ATmega103__)
- /* Macro for ATmega103 compatibility */
+ #define AVR_HAS_UART1 0
#define UCSR0B UCR
#define UDR0 UDR
#define UCSR0A USR
#endif
-/* Transmission fill byte */
-#define SER_FILL_BYTE 0xAA
-
+/* From the high-level serial driver */
+extern struct Serial ser_handles[SER_CNT];
-static void uart0_enabletxirq(UNUSED(struct SerialHardware *, ctx))
+/*!
+ * Internal hardware state structure
+ *
+ * \a sending var is true if we are transmitting.
+ * SPI note: this flag is necessary because the SPI sends and receives bytes
+ * at the same time and the SPI IRQ is unique for send/receive.
+ * The only way to start transmission is to write data in SPDR (this
+ * is done by spi_starttx()). We do this *only* if a transfer is
+ * not already started.
+ *
+ * For the USARTs the \a sending flag is useful for taking specific
+ * actions before sending a burst of data, at the start of a trasmission
+ * but not before every char sent.
+ */
+struct AvrSerial
{
-#if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 0)
- UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN) | BV(UCSZ2);
-#else
- UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+ struct SerialHardware hw;
+ volatile bool sending;
+};
+
+/*
+ * These are to trick GCC into *not* using
+ * absolute addressing mode when accessing
+ * ser_handles, which is very expensive.
+ *
+ * Accessing through these pointers generates
+ * much shorter (and hopefully faster) code.
+ */
+struct Serial *ser_uart0 = &ser_handles[SER_UART0];
+#if AVR_HAS_UART1
+struct Serial *ser_uart1 = &ser_handles[SER_UART1];
#endif
-}
+struct Serial *ser_spi = &ser_handles[SER_SPI];
-static void uart0_init(struct SerialHardware *_hw, struct Serial *ser)
-{
- struct AvrSerial *hw = (struct AvrSerial *)_hw;
- hw->serial = ser;
-#if defined(ARCH_BOARD_KS) && (ARCH & ARCH_BOARD_KS)
- /* Set TX port as input with pull-up enabled to avoid
- noise on the remote RX when TX is disabled. */
- cpuflags_t flags;
- DISABLE_IRQSAVE(flags);
- DDRE &= ~BV(PORTE1);
- PORTE |= BV(PORTE1);
- ENABLE_IRQRESTORE(flags);
-#endif /* ARCH_BOARD_KS */
-
-#if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 0)
- /*!
- * Set multiprocessor mode and 9 bit data frame.
- * The receiver keep MPCM bit always on. When useful data
- * is trasmitted the ninth bit is set and the receiver receive
- * the frame.
- * When useless fill bytes are sent the ninth bit is cleared
- * and the receiver will ignore them.
- */
- UCSR0A = BV(MPCM);
- UCSR0B = BV(RXCIE) | BV(RXEN) | BV(UCSZ2);
-#else
- UCSR0B = BV(RXCIE) | BV(RXEN);
-#endif
+/*
+ * Callbacks
+ */
+static void uart0_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
+{
+ SER_UART0_BUS_TXINIT;
RTS_ON;
}
-static void uart0_cleanup(UNUSED(struct SerialHardware *, ctx))
+static void uart0_cleanup(UNUSED(struct SerialHardware *, _hw))
{
UCSR0B = 0;
}
-static void uart0_setbaudrate(UNUSED(struct SerialHardware *, ctx), unsigned long rate)
+static void uart0_enabletxirq(struct SerialHardware *_hw)
+{
+ struct AvrSerial *hw = (struct AvrSerial *)_hw;
+
+ /*
+ * WARNING: racy code here! The tx interrupt
+ * sets hw->sending to false when it runs with
+ * an empty fifo. The order of the statements
+ * in the if-block matters.
+ */
+ if (!hw->sending)
+ {
+ hw->sending = true;
+ SER_UART0_BUS_TXBEGIN;
+ }
+}
+
+static void uart0_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
{
/* Compute baud-rate period */
uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
- DB(kprintf("uart0_setbaudrate(rate=%ld): period=%d\n", rate, period);)
#ifndef __AVR_ATmega103__
UBRR0H = (period) >> 8;
#endif
UBRR0L = (period);
+
+ DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
}
-static void uart0_setparity(UNUSED(struct SerialHardware *, ctx), int parity)
+static void uart0_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
{
#ifndef __AVR_ATmega103__
UCSR0C |= (parity) << UPM0;
#endif
}
-#ifdef AVR_HAS_UART1
+#if AVR_HAS_UART1
-static void uart1_enabletxirq(UNUSED(struct SerialHardware *, ctx))
+static void uart1_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
{
-#if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 1)
- UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN) | BV(UCSZ2);
-#else
- UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
-#endif
+ SER_UART1_BUS_TXINIT;
+ RTS_ON;
+ SER_STROBE_INIT;
}
-static void uart1_init(struct SerialHardware *_hw, struct Serial *ser)
+static void uart1_cleanup(UNUSED(struct SerialHardware *, _hw))
{
- struct AvrSerial *hw = (struct AvrSerial *)_hw;
- hw->serial = ser;
-
- /* Set TX port as input with pull-up enabled to avoid
- * noise on the remote RX when TX is disabled */
- cpuflags_t flags;
- DISABLE_IRQSAVE(flags);
- DDRD &= ~BV(PORTD3);
- PORTD |= BV(PORTD3);
- ENABLE_IRQRESTORE(flags);
-
-#if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 1)
- /*! See comment in uart0_init() */
- UCSR1A = BV(MPCM);
- UCSR1B = BV(RXCIE) | BV(RXEN) | BV(UCSZ2);
-#else
- UCSR1B = BV(RXCIE) | BV(RXEN);
-#endif
-
- RTS_ON;
+ UCSR1B = 0;
}
-static void uart1_cleanup(UNUSED(struct SerialHardware *, ctx))
+static void uart1_enabletxirq(struct SerialHardware *_hw)
{
- UCSR1B = 0;
+ struct AvrSerial *hw = (struct AvrSerial *)_hw;
+
+ /*
+ * WARNING: racy code here! The tx interrupt
+ * sets hw->sending to false when it runs with
+ * an empty fifo. The order of the statements
+ * in the if-block matters.
+ */
+ if (!hw->sending)
+ {
+ hw->sending = true;
+ SER_UART1_BUS_TXBEGIN;
+ }
}
-static void uart1_setbaudrate(UNUSED(struct SerialHardware *, ctx), unsigned long rate)
+static void uart1_setbaudrate(UNUSED(struct SerialHardware *, _hw), unsigned long rate)
{
/* Compute baud-rate period */
uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
- DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
UBRR1H = (period) >> 8;
UBRR1L = (period);
+
+ DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
}
-static void uart1_setparity(UNUSED(struct SerialHardware *, ctx), int parity)
+static void uart1_setparity(UNUSED(struct SerialHardware *, _hw), int parity)
{
- // FIXME: move somewhere else
- UCSR1C |= BV(USBS1); // 2 stop bits
UCSR1C |= (parity) << UPM0;
}
#endif // AVR_HAS_UART1
-
-static void spi_init(struct SerialHardware *_hw, struct Serial *ser)
+static void spi_init(UNUSED(struct SerialHardware *, _hw), UNUSED(struct Serial *, ser))
{
- struct AvrSerial *hw = (struct AvrSerial *)_hw;
- hw->serial = ser;
-
/*
* Set MOSI and SCK ports out, MISO in.
*
* active the I/O port are overrided.
* This is *blatantly FALSE*.
*
- * Moreover the MISO pin on the board_kc *must* be in high impedance
+ * Moreover, the MISO pin on the board_kc *must* be in high impedance
* state even when the SPI is off, because the line is wired together
* with the KBus serial RX, and the transmitter of the slave boards
- * could not be able to drive the line.
+ * would be unable to drive the line.
*/
SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
SPI_DDR &= ~BV(SPI_MISO_BIT);
SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
}
-static void spi_cleanup(UNUSED(struct SerialHardware *, ctx))
+static void spi_cleanup(UNUSED(struct SerialHardware *, _hw))
{
SPCR = 0;
/* Set all pins as inputs */
SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
}
-static void spi_setbaudrate(UNUSED(struct SerialHardware *, ctx), UNUSED(unsigned long, rate))
+static void spi_starttx(struct SerialHardware *_hw)
{
- // Do nothing
+ struct AvrSerial *hw = (struct AvrSerial *)_hw;
+
+ cpuflags_t flags;
+ DISABLE_IRQSAVE(flags);
+
+ /* Send data only if the SPI is not already transmitting */
+ if (!hw->sending && !fifo_isempty(&ser_spi->txfifo))
+ {
+ hw->sending = true;
+ SPDR = fifo_pop(&ser_spi->txfifo);
+ }
+
+ ENABLE_IRQRESTORE(flags);
}
-static void spi_setparity(UNUSED(struct SerialHardware *, ctx), UNUSED(int, parity))
+static void spi_setbaudrate(UNUSED(struct SerialHardware *, _hw), UNUSED(unsigned long, rate))
{
- // Do nothing
+ // nop
+}
+
+static void spi_setparity(UNUSED(struct SerialHardware *, _hw), UNUSED(int, parity))
+{
+ // nop
}
-#if defined(CONFIG_SER_HW_HANDSHAKE)
+
+/*
+ * High-level interface data structures
+ */
+static const struct SerialHardwareVT UART0_VT =
+{
+ .init = uart0_init,
+ .cleanup = uart0_cleanup,
+ .setbaudrate = uart0_setbaudrate,
+ .setparity = uart0_setparity,
+ .enabletxirq = uart0_enabletxirq,
+};
+
+#if AVR_HAS_UART1
+static const struct SerialHardwareVT UART1_VT =
+{
+ .init = uart1_init,
+ .cleanup = uart1_cleanup,
+ .setbaudrate = uart1_setbaudrate,
+ .setparity = uart1_setparity,
+ .enabletxirq = uart1_enabletxirq,
+};
+#endif // AVR_HAS_UART1
+
+static const struct SerialHardwareVT SPI_VT =
+{
+ .init = spi_init,
+ .cleanup = spi_cleanup,
+ .setbaudrate = spi_setbaudrate,
+ .setparity = spi_setparity,
+ .enabletxirq = spi_starttx,
+};
+
+static struct AvrSerial UARTDescs[SER_CNT] =
+{
+ {
+ .hw = { .table = &UART0_VT },
+ .sending = false,
+ },
+#if AVR_HAS_UART1
+ {
+ .hw = { .table = &UART1_VT },
+ .sending = false,
+ },
+#endif
+ {
+ .hw = { .table = &SPI_VT },
+ .sending = false,
+ }
+};
+
+struct SerialHardware* ser_hw_getdesc(int unit)
+{
+ ASSERT(unit < SER_CNT);
+ return &UARTDescs[unit].hw;
+}
+
+
+
+/*
+ * Interrupt handlers
+ */
+
+#if CONFIG_SER_HWHANDSHAKE
//! This interrupt is triggered when the CTS line goes high
SIGNAL(SIG_CTS)
cbi(EIMSK, EIMSKB_CTS);
}
-#endif // CONFIG_SER_HW_HANDSHAKE
+#endif // CONFIG_SER_HWHANDSHAKE
/*!
*/
SIGNAL(SIG_UART0_DATA)
{
- if (fifo_isempty(&ser_handles[SER_UART0].txfifo))
+ SER_STROBE_ON;
+
+ struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
+
+ if (fifo_isempty(txfifo))
{
-#if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 0)
- /*
- * To avoid audio interference: always transmit useless char.
- * Send the byte with the ninth bit cleared, the receiver in MCPM mode
- * will ignore it.
- */
- UCSR0B &= ~BV(TXB8);
- UDR0 = SER_FILL_BYTE;
-#else
- /* Disable UDR empty interrupt and transmitter */
- UCSR0B = BV(RXCIE) | BV(RXEN);
+ SER_UART0_BUS_TXEND;
+#ifndef SER_UART0_BUS_TXOFF
+ UARTDescs[SER_UART0].sending = false;
#endif
}
-#if defined(CONFIG_SER_HWHANDSHAKE)
- else if (IS_CTS_OFF)
+#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
+ else if (!IS_CTS_ON)
{
- // disable rx interrupt and tx, enable CTS interrupt
+ // Disable rx interrupt and tx, enable CTS interrupt
+ // UNTESTED
UCSR0B = BV(RXCIE) | BV(RXEN);
sbi(EIFR, EIMSKB_CTS);
sbi(EIMSK, EIMSKB_CTS);
}
-#endif // CONFIG_SER_HWHANDSHAKE
+#endif
else
{
-#if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 0)
- /* Send with ninth bit set. Receiver in MCPM mode will receive it */
- UCSR0B |= BV(TXB8);
-#endif
- UDR0 = fifo_pop(&ser_handles[SER_UART0].txfifo);
+ char c = fifo_pop(txfifo);
+ SER_UART0_BUS_TXCHAR(c);
+ }
+
+ SER_STROBE_OFF;
+}
+
+#ifdef SER_UART0_BUS_TXOFF
+/*!
+ * Serial port 0 TX complete interrupt handler.
+ *
+ * This IRQ is usually disabled. The UDR-empty interrupt
+ * enables it when there's no more data to transmit.
+ * We need to wait until the last character has been
+ * transmitted before switching the 485 transceiver to
+ * receive mode.
+ *
+ * The txfifo might have been refilled by putchar() while
+ * we were waiting for the transmission complete interrupt.
+ * In this case, we must restart the UDR empty interrupt,
+ * otherwise we'd stop the serial port with some data
+ * still pending in the buffer.
+ */
+SIGNAL(SIG_UART0_TRANS)
+{
+ SER_STROBE_ON;
+
+ struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
+ if (fifo_isempty(txfifo))
+ {
+ SER_UART0_BUS_TXOFF;
+ UARTDescs[SER_UART0].sending = false;
}
+ else
+ UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+
+ SER_STROBE_OFF;
}
+#endif /* SER_UART0_BUS_TXOFF */
-#ifdef AVR_HAS_UART1
+#if AVR_HAS_UART1
/*!
* Serial 1 TX interrupt handler
*/
SIGNAL(SIG_UART1_DATA)
{
- if (fifo_isempty(&ser_handles[SER_UART1].txfifo))
+ SER_STROBE_ON;
+
+ struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
+
+ if (fifo_isempty(txfifo))
{
-#if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 1)
- /*
- * To avoid audio interference: always transmit useless char.
- * Send the byte with the ninth bit cleared, the receiver in MCPM mode
- * will ignore it.
- */
- UCSR1B &= ~BV(TXB8);
- UDR1 = SER_FILL_BYTE;
-#else
- /* Disable UDR empty interrupt and transmitter */
- UCSR1B = BV(RXCIE) | BV(RXEN);
+ SER_UART1_BUS_TXEND;
+#ifndef SER_UART1_BUS_TXOFF
+ UARTDescs[SER_UART1].sending = false;
#endif
}
-#if defined(CONFIG_SER_HWHANDSHAKE)
- else if (IS_CTS_OFF)
+#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
+ else if (!IS_CTS_ON)
{
- // disable rx interrupt and tx, enable CTS interrupt
+ // Disable rx interrupt and tx, enable CTS interrupt
+ // UNTESTED
UCSR1B = BV(RXCIE) | BV(RXEN);
sbi(EIFR, EIMSKB_CTS);
sbi(EIMSK, EIMSKB_CTS);
}
-#endif // CONFIG_SER_HWHANDSHAKE
+#endif
else
{
-#if defined(CONFIG_SER_TXFILL) && (CONFIG_KBUS_SERIAL_PORT == 1)
- /* Send with ninth bit set. Receiver in MCPM mode will receive it */
- UCSR1B |= BV(TXB8);
-#endif
- UDR1 = fifo_pop(&ser_handles[SER_UART1].txfifo);
+ char c = fifo_pop(txfifo);
+ SER_UART1_BUS_TXCHAR(c);
}
+
+ SER_STROBE_OFF;
}
+
+#ifdef SER_UART1_BUS_TXOFF
+/*!
+ * Serial port 1 TX complete interrupt handler.
+ *
+ * \sa port 0 TX complete handler.
+ */
+SIGNAL(SIG_UART1_TRANS)
+{
+ SER_STROBE_ON;
+
+ struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
+ if (fifo_isempty(txfifo))
+ {
+ SER_UART1_BUS_TXOFF;
+ UARTDescs[SER_UART1].sending = false;
+ }
+ else
+ UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+
+ SER_STROBE_OFF;
+}
+#endif /* SER_UART1_BUS_TXOFF */
+
#endif // AVR_HAS_UART1
*/
SIGNAL(SIG_UART0_RECV)
{
+ SER_STROBE_ON;
+
/* Disable Recv complete IRQ */
UCSR0B &= ~BV(RXCIE);
ENABLE_INTS;
/* Should be read before UDR */
- ser_handles[SER_UART0].status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
+ ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
/* To clear the RXC flag we must _always_ read the UDR even when we're
* not going to accept the incoming data, otherwise a new interrupt
* will occur once the handler terminates.
*/
char c = UDR0;
+ struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
- if (fifo_isfull(&ser_handles[SER_UART0].rxfifo))
- ser_handles[SER_UART0].status |= SERRF_RXFIFOOVERRUN;
+ if (fifo_isfull(rxfifo))
+ ser_uart0->status |= SERRF_RXFIFOOVERRUN;
else
{
- fifo_push(&ser_handles[SER_UART0].rxfifo, c);
-#if defined(CONFIG_SER_HW_HANDSHAKE)
- if (fifo_isfull(&ser_handles[SER_UART0].rxfifo))
+ fifo_push(rxfifo, c);
+#if CONFIG_SER_HWHANDSHAKE
+ if (fifo_isfull(rxfifo))
RTS_OFF;
#endif
}
+
/* Reenable receive complete int */
UCSR0B |= BV(RXCIE);
+
+ SER_STROBE_OFF;
}
-#ifdef AVR_HAS_UART1
+#if AVR_HAS_UART1
/*!
* Serial 1 RX complete interrupt handler.
*/
SIGNAL(SIG_UART1_RECV)
{
+ SER_STROBE_ON;
+
/* Disable Recv complete IRQ */
UCSR1B &= ~BV(RXCIE);
ENABLE_INTS;
/* Should be read before UDR */
- ser_handles[SER_UART1].status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
+ ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
/* To avoid an IRQ storm, we must _always_ read the UDR even when we're
* not going to accept the incoming data
*/
char c = UDR1;
+ struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
- if (fifo_isfull(&ser_handles[SER_UART1].rxfifo))
- ser_handles[SER_UART1].status |= SERRF_RXFIFOOVERRUN;
+ if (fifo_isfull(rxfifo))
+ ser_uart1->status |= SERRF_RXFIFOOVERRUN;
else
{
- fifo_push(&ser_handles[SER_UART1].rxfifo, c);
-#if defined(CONFIG_SER_HW_HANDSHAKE)
- if (fifo_isfull(&ser_handles[SER_UART1].rxfifo))
+ fifo_push(rxfifo, c);
+#if CONFIG_SER_HWHANDSHAKE
+ if (fifo_isfull(rxfifo))
RTS_OFF;
#endif
}
/* Reenable receive complete int */
UCSR1B |= BV(RXCIE);
+
+ SER_STROBE_OFF;
}
#endif // AVR_HAS_UART1
-/*
- * SPI Flag: true if we are transmitting/receiving with the SPI.
- *
- * This kludge is necessary because the SPI sends and receives bytes
- * at the same time and the SPI IRQ is unique for send/receive.
- * The only way to start transmission is to write data in SPDR (this
- * is done by spi_starttx()). We do this *only* if a transfer is
- * not already started.
- */
-static volatile bool spi_sending = false;
-
-static void spi_starttx(UNUSED(struct SerialHardware *, ctx))
-{
- cpuflags_t flags;
-
- DISABLE_IRQSAVE(flags);
-
- /* Send data only if the SPI is not already transmitting */
- if (!spi_sending && !fifo_isempty(&ser_handles[SER_SPI].txfifo))
- {
- SPDR = fifo_pop(&ser_handles[SER_SPI].txfifo);
- spi_sending = true;
- }
-
- ENABLE_IRQRESTORE(flags);
-}
-
/*!
* SPI interrupt handler
*/
SIGNAL(SIG_SPI)
{
/* Read incoming byte. */
- if (!fifo_isfull(&ser_handles[SER_SPI].rxfifo))
- fifo_push(&ser_handles[SER_SPI].rxfifo, SPDR);
+ if (!fifo_isfull(&ser_spi->rxfifo))
+ fifo_push(&ser_spi->rxfifo, SPDR);
/*
* FIXME
else
- ser_handles[SER_SPI].status |= SERRF_RXFIFOOVERRUN;
+ ser_spi->status |= SERRF_RXFIFOOVERRUN;
*/
/* Send */
- if (!fifo_isempty(&ser_handles[SER_SPI].txfifo))
- SPDR = fifo_pop(&ser_handles[SER_SPI].txfifo);
+ if (!fifo_isempty(&ser_spi->txfifo))
+ SPDR = fifo_pop(&ser_spi->txfifo);
else
- spi_sending = false;
-}
-
-
-static const struct SerialHardwareVT UART0_VT =
-{
- .init = uart0_init,
- .cleanup = uart0_cleanup,
- .setbaudrate = uart0_setbaudrate,
- .setparity = uart0_setparity,
- .enabletxirq = uart0_enabletxirq,
-};
-
-#ifdef AVR_HAS_UART1
-static const struct SerialHardwareVT UART1_VT =
-{
- .init = uart1_init,
- .cleanup = uart1_cleanup,
- .setbaudrate = uart1_setbaudrate,
- .setparity = uart1_setparity,
- .enabletxirq = uart1_enabletxirq,
-};
-#endif // AVR_HAS_UART1
-
-static const struct SerialHardwareVT SPI_VT =
-{
- .init = spi_init,
- .cleanup = spi_cleanup,
- .setbaudrate = spi_setbaudrate,
- .setparity = spi_setparity,
- .enabletxirq = spi_starttx,
-};
-
-static struct AvrSerial UARTDescs[SER_CNT] =
-{
- { .hw = { .table = &UART0_VT } },
-#ifdef AVR_HAS_UART1
- { .hw = { .table = &UART1_VT } },
-#endif // AVR_HAS_UART1
- { .hw = { .table = &SPI_VT } },
-};
-
-struct SerialHardware* ser_hw_getdesc(int unit)
-{
- ASSERT(unit < SER_CNT);
- return &UARTDescs[unit].hw;
+ UARTDescs[SER_SPI].sending = false;
}