/*#*
*#* $Log$
+ *#* Revision 1.24 2005/01/14 00:49:16 aleph
+ *#* Rename callbacks; SerialHardwareVT.txSending: New callback; Add SPI_BUS macros.
+ *#*
+ *#* Revision 1.23 2005/01/11 18:09:07 aleph
+ *#* Add ATmega8 SPI port definitions; Fix transmit complete IRQ bug; add strobe macros to uart1 and spi
+ *#*
*#* Revision 1.22 2004/12/31 17:47:45 bernie
*#* Rename UNUSED() to UNUSED_ARG().
*#*
/*\}*/
+/*!
+ * \name Overridable SPI hooks
+ *
+ * These can be redefined in hw.h to implement
+ * special bus policies such as slave select pin handling, etc.
+ *
+ * \{
+ */
+#ifndef SER_SPI_BUS_TXINIT
+ /*!
+ * \def SER_SPI_BUS_TXINIT
+ *
+ * Default TXINIT macro - invoked in spi_init()
+ * The default is no action.
+ */
+ #define SER_SPI_BUS_TXINIT
+#endif
+
+#ifndef SER_SPI_BUS_TXCLOSE
+ /*!
+ * \def SER_SPI_BUS_TXCLOSE
+ *
+ * Invoked after the last character has been transmitted.
+ * The default is no action.
+ */
+ #define SER_SPI_BUS_TXCLOSE
+#endif
+/*\}*/
+
+
/* SPI port and pin configuration */
-#define SPI_PORT PORTB
-#define SPI_DDR DDRB
-#define SPI_SCK_BIT PB1
-#define SPI_MOSI_BIT PB2
-#define SPI_MISO_BIT PB3
+#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
+ #define SPI_PORT PORTB
+ #define SPI_DDR DDRB
+ #define SPI_SCK_BIT PB1
+ #define SPI_MOSI_BIT PB2
+ #define SPI_MISO_BIT PB3
+#elif CPU_AVR_ATMEGA8
+ #define SPI_PORT PORTB
+ #define SPI_DDR DDRB
+ #define SPI_SCK_BIT PB5
+ #define SPI_MOSI_BIT PB3
+ #define SPI_MISO_BIT PB4
+#else
+ #error Unknown architecture
+#endif
/* USART register definitions */
#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128
#define UBRR0H UBRRH
#define SIG_UART0_DATA SIG_UART_DATA
#define SIG_UART0_RECV SIG_UART_RECV
+ #define SIG_UART0_TRANS SIG_UART_TRANS
#elif CPU_AVR_ATMEGA103
#define AVR_HAS_UART1 0
#define UCSR0B UCR
#define UBRR0L UBRR
#define SIG_UART0_DATA SIG_UART_DATA
#define SIG_UART0_RECV SIG_UART_RECV
+ #define SIG_UART0_TRANS SIG_UART_TRANS
#else
#error Unknown architecture
#endif
{
SER_UART0_BUS_TXINIT;
RTS_ON;
+ SER_STROBE_INIT;
}
static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
SPI_DDR &= ~BV(SPI_MISO_BIT);
/* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
+
+ SER_SPI_BUS_TXINIT;
+
+ SER_STROBE_INIT;
}
static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
{
SPCR = 0;
+
+ SER_SPI_BUS_TXCLOSE;
+
/* Set all pins as inputs */
SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
}
// nop
}
+static bool tx_sending(struct SerialHardware* _hw)
+{
+ struct AvrSerial *hw = (struct AvrSerial *)_hw;
+ return hw->sending;
+}
+
+
// FIXME: move into compiler.h? Ditch?
#if COMPILER_C99
{
C99INIT(init, uart0_init),
C99INIT(cleanup, uart0_cleanup),
- C99INIT(setbaudrate, uart0_setbaudrate),
- C99INIT(setparity, uart0_setparity),
- C99INIT(enabletxirq, uart0_enabletxirq),
+ C99INIT(setBaudrate, uart0_setbaudrate),
+ C99INIT(setParity, uart0_setparity),
+ C99INIT(txStart, uart0_enabletxirq),
+ C99INIT(txSending, tx_sending),
};
#if AVR_HAS_UART1
{
C99INIT(init, uart1_init),
C99INIT(cleanup, uart1_cleanup),
- C99INIT(setbaudrate, uart1_setbaudrate),
- C99INIT(setparity, uart1_setparity),
- C99INIT(enabletxirq, uart1_enabletxirq),
+ C99INIT(setBaudrate, uart1_setbaudrate),
+ C99INIT(setParity, uart1_setparity),
+ C99INIT(txStart, uart1_enabletxirq),
+ C99INIT(txSending, tx_sending),
};
#endif // AVR_HAS_UART1
{
C99INIT(init, spi_init),
C99INIT(cleanup, spi_cleanup),
- C99INIT(setbaudrate, spi_setbaudrate),
- C99INIT(setparity, spi_setparity),
- C99INIT(enabletxirq, spi_starttx),
+ C99INIT(setBaudrate, spi_setbaudrate),
+ C99INIT(setParity, spi_setparity),
+ C99INIT(txStart, spi_starttx),
+ C99INIT(txSending, tx_sending),
};
static struct AvrSerial UARTDescs[SER_CNT] =
*/
SIGNAL(SIG_SPI)
{
+ SER_STROBE_ON;
+
/* Read incoming byte. */
if (!fifo_isfull(&ser_spi->rxfifo))
fifo_push(&ser_spi->rxfifo, SPDR);
SPDR = fifo_pop(&ser_spi->txfifo);
else
UARTDescs[SER_SPI].sending = false;
+
+ SER_STROBE_OFF;
}