* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
- * Copyright 2003, 2004, 2006 Develer S.r.l. (http://www.develer.com/)
+ * Copyright 2003, 2004, 2006, 2009 Develer S.r.l. (http://www.develer.com/)
* Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
*
* -->
*
* \version $Id$
*
+ * \author Andrea Grandi <andrea@develer.com>
* \author Daniele Basile <asterix@develer.com>
*/
#include <avr/io.h>
+/**
+ * Mapping sipo connection on board.
+ * See schematics for more info.
+ */
+typedef enum SipoMap
+{
+ TRIFACE_DOUT = 0,
+
+ SIPO_CNT
+} SipoMap;
+
+
+
//Set output pin for sipo
-#define SCK_OUT (DDRB |= BV(PB1)) // Load clock pin
-#define SOUT_OUT (DDRB |= BV(PB2)) // Serial in pin
-#define SLOAD_OUT (DDRB |= BV(PB3)) // Store clock pin
+#define SCK_OUT (DDRB |= BV(PB1)) // Shift register clock input pin
+#define SOUT_OUT (DDRB |= BV(PB2)) // Serial data input pin
+#define SLOAD_OUT (DDRB |= BV(PB3)) // Storage register clock input pin
#define OE_OUT (DDRG |= BV(PG3)) // Output enable pin
//Define output level
#define OE_LOW (PORTG &= BV(PG3))
/**
- * Define the procedure to set one bit low/hight to
- * serial input in sipo device.
+ * Define the macros needed to set the serial input bit of SIPO device
+ * low or high.
*/
#define SIPO_SI_HIGH() SOUT_OUT_HIGH
#define SIPO_SI_LOW() SOUT_OUT_LOW
* Drive pin to load the bit, presented in serial-in pin,
* into sipo shift register.
*/
-#define SIPO_SI_CLOCK() \
+#define SIPO_SI_CLOCK(clk_pol) \
do{ \
+ (void)clk_pol; \
SCK_HIGH; \
SCK_LOW; \
}while(0)
/**
* Clock the content of shift register to output.
*/
-#define SIPO_LOAD() \
+#define SIPO_LOAD(device, load_pol) \
do { \
+ (void)device; \
+ (void)load_pol; \
SLOAD_OUT_HIGH; \
SLOAD_OUT_LOW; \
}while(0)
*/
#define SIPO_ENABLE() OE_LOW;
+/**
+ * Set logic level for load signal
+ */
+#define SIPO_SET_LD_LEVEL(device, load_pol) \
+ do { \
+ (void)device; \
+ if(load_pol) \
+ SLOAD_OUT_HIGH; \
+ else \
+ SLOAD_OUT_LOW; \
+ } while (0)
+
+
+/**
+ * Sel logic level for clock signal
+ */
+#define SIPO_SET_CLK_LEVEL(clock_pol) \
+ do { \
+ if(clock_pol) \
+ SCK_HIGH; \
+ else \
+ SCK_LOW; \
+ } while (0)
+
+#define SIPO_SET_SI_LEVEL() SIPO_SI_LOW()
/**
- * Do anything that needed to init sipo pins.
+ * Do everything needed in order to init the SIPO pins.
*/
#define SIPO_INIT_PIN() \
do { \