X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=inline;f=drv%2Fser_avr.c;h=02a3427e0ac185a3a7be92eac099b67c9ea20965;hb=f4c89bc436e098ec88d46c1cf57f134814f35ee3;hp=e31a77dcb30794d165f53aab6e31833cb2d704c4;hpb=76c53bfa0136be55cf17e57b1ee098e5dfeefa70;p=bertos.git

diff --git a/drv/ser_avr.c b/drv/ser_avr.c
index e31a77dc..02a3427e 100755
--- a/drv/ser_avr.c
+++ b/drv/ser_avr.c
@@ -1,4 +1,4 @@
-/*!
+/**
  * \file
  * <!--
  * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
@@ -38,6 +38,21 @@
 
 /*#*
  *#* $Log$
+ *#* Revision 1.33  2006/09/13 18:21:24  bernie
+ *#* Add configurable SPI pin mapping.
+ *#*
+ *#* Revision 1.32  2006/07/19 12:56:26  bernie
+ *#* Convert to new Doxygen style.
+ *#*
+ *#* Revision 1.31  2006/05/18 00:37:29  bernie
+ *#* Use hw_ser.h instead of ubiquitous hw.h.
+ *#*
+ *#* Revision 1.30  2006/02/17 22:23:06  bernie
+ *#* Update POSIX serial emulator.
+ *#*
+ *#* Revision 1.29  2005/11/27 23:31:48  bernie
+ *#* Support avr-libc 1.4.
+ *#*
  *#* Revision 1.28  2005/11/04 16:20:02  bernie
  *#* Fix reference to README.devlib in header.
  *#*
@@ -120,31 +135,35 @@
 
 #include "ser.h"
 #include "ser_p.h"
-#include <cfg/config.h>
-#include "hw.h"  /* Required for bus macros overrides */
+#include "hw_ser.h"  /* Required for bus macros overrides */
+#include <appconfig.h>
 
 #include <cfg/debug.h>
 #include <drv/timer.h>
 #include <mware/fifobuf.h>
 
-#include <avr/signal.h>
 #include <avr/io.h>
+#if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL)
+	#include <avr/interrupt.h>
+#else
+	#include <avr/signal.h>
+#endif
 
 
 #if !CONFIG_SER_HWHANDSHAKE
-	/*!
+	/**
 	 * \name Hardware handshake (RTS/CTS).
 	 * \{
 	 */
 	#define RTS_ON      do {} while (0)
 	#define RTS_OFF     do {} while (0)
 	#define IS_CTS_ON   true
-	#define EIMSKF_CTS  0 /*!< Dummy value, must be overridden */
+	#define EIMSKF_CTS  0 /**< Dummy value, must be overridden */
 	/*\}*/
 #endif
 
 
-/*!
+/**
  * \name Overridable serial bus hooks
  *
  * These can be redefined in hw.h to implement
@@ -165,7 +184,7 @@
  * \{
  */
 #ifndef SER_UART0_BUS_TXINIT
-	/*!
+	/**
 	 * Default TXINIT macro - invoked in uart0_init()
 	 *
 	 * - Enable both the receiver and the transmitter
@@ -177,7 +196,7 @@
 #endif
 
 #ifndef SER_UART0_BUS_TXBEGIN
-	/*!
+	/**
 	 * Invoked before starting a transmission
 	 *
 	 * - Enable both the receiver and the transmitter
@@ -189,7 +208,7 @@
 #endif
 
 #ifndef SER_UART0_BUS_TXCHAR
-	/*!
+	/**
 	 * Invoked to send one character.
 	 */
 	#define SER_UART0_BUS_TXCHAR(c) do { \
@@ -198,7 +217,7 @@
 #endif
 
 #ifndef SER_UART0_BUS_TXEND
-	/*!
+	/**
 	 * Invoked as soon as the txfifo becomes empty
 	 *
 	 * - Keep both the receiver and the transmitter enabled
@@ -211,7 +230,7 @@
 #endif
 
 #ifndef SER_UART0_BUS_TXOFF
-	/*!
+	/**
 	 * \def SER_UART0_BUS_TXOFF
 	 *
 	 * Invoked after the last character has been transmitted
@@ -224,31 +243,31 @@
 #endif
 
 #ifndef SER_UART1_BUS_TXINIT
-	/*! \sa SER_UART0_BUS_TXINIT */
+	/** \sa SER_UART0_BUS_TXINIT */
 	#define SER_UART1_BUS_TXINIT do { \
 		UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
 	} while (0)
 #endif
 #ifndef SER_UART1_BUS_TXBEGIN
-	/*! \sa SER_UART0_BUS_TXBEGIN */
+	/** \sa SER_UART0_BUS_TXBEGIN */
 	#define SER_UART1_BUS_TXBEGIN do { \
 		UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); \
 	} while (0)
 #endif
 #ifndef SER_UART1_BUS_TXCHAR
-	/*! \sa SER_UART0_BUS_TXCHAR */
+	/** \sa SER_UART0_BUS_TXCHAR */
 	#define SER_UART1_BUS_TXCHAR(c) do { \
 		UDR1 = (c); \
 	} while (0)
 #endif
 #ifndef SER_UART1_BUS_TXEND
-	/*! \sa SER_UART0_BUS_TXEND */
+	/** \sa SER_UART0_BUS_TXEND */
 	#define SER_UART1_BUS_TXEND do { \
 		UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); \
 	} while (0)
 #endif
 #ifndef SER_UART1_BUS_TXOFF
-	/*!
+	/**
 	 * \def SER_UART1_BUS_TXOFF
 	 *
 	 * \see SER_UART0_BUS_TXOFF
@@ -260,7 +279,7 @@
 /*\}*/
 
 
-/*!
+/**
  * \name Overridable SPI hooks
  *
  * These can be redefined in hw.h to implement
@@ -269,7 +288,7 @@
  * \{
  */
 #ifndef SER_SPI_BUS_TXINIT
-	/*!
+	/**
 	 * Default TXINIT macro - invoked in spi_init()
 	 * The default is no action.
 	 */
@@ -277,7 +296,7 @@
 #endif
 
 #ifndef SER_SPI_BUS_TXCLOSE
-	/*!
+	/**
 	 * Invoked after the last character has been transmitted.
 	 * The default is no action.
 	 */
@@ -290,12 +309,14 @@
 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
 	#define SPI_PORT      PORTB
 	#define SPI_DDR       DDRB
+	#define SPI_SS_BIT    PB0
 	#define SPI_SCK_BIT   PB1
 	#define SPI_MOSI_BIT  PB2
 	#define SPI_MISO_BIT  PB3
 #elif CPU_AVR_ATMEGA8
 	#define SPI_PORT      PORTB
 	#define SPI_DDR       DDRB
+	#define SPI_SS_BIT    PB2
 	#define SPI_SCK_BIT   PB5
 	#define SPI_MOSI_BIT  PB3
 	#define SPI_MISO_BIT  PB4
@@ -331,7 +352,7 @@
 #endif
 
 
-/*!
+/**
  * \def CONFIG_SER_STROBE
  *
  * This is a debug facility that can be used to
@@ -362,7 +383,7 @@ static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
 
 
-/*!
+/**
  * Internal hardware state structure
  *
  * The \a sending variable is true while the transmission
@@ -519,11 +540,60 @@ static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct
 	 * with the KBus serial RX, and the transmitter of the slave boards
 	 * would be unable to drive the line.
 	 */
-	SPI_DDR |= BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT);
-	SPI_DDR &= ~BV(SPI_MISO_BIT);
-	/* Enable SPI, IRQ on, Master, CPU_CLOCK/16 */
-	SPCR = BV(SPE) | BV(SPIE) | BV(MSTR) | BV(SPR0);
+	ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
+
+	/*
+	 * If the SPI master mode is activated and the SS pin is in input and tied low,
+	 * the SPI hardware will automatically switch to slave mode!
+	 * For proper communication this pins should therefore be:
+	 * - as output
+	 * - as input but tied high forever!
+	 * This driver set the pin as output.
+	 */
+	#warning SPI SS pin set as output for proper operation, check schematics for possible conflicts.
+	ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
 
+	ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
+	/* Enable SPI, IRQ on, Master */
+	SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
+
+	/* Set data order */
+	#if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
+		SPCR |= BV(DORD);
+	#endif
+
+	/* Set SPI clock rate */
+	#if CONFIG_SPI_CLOCK_DIV == 128
+		SPCR |= (BV(SPR1) | BV(SPR0));
+	#elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
+		SPCR |= BV(SPR1);
+	#elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
+		SPCR |= BV(SPR0);
+	#elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
+		// SPR0 & SDPR1 both at 0
+	#else
+		#error Unsupported SPI clock division factor.
+	#endif
+
+	/* Set SPI2X bit (spi double frequency) */
+	#if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
+	  || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
+		SPSR &= ~BV(SPI2X);
+	#elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
+		SPSR |= BV(SPI2X);
+	#else
+		#error Unsupported SPI clock division factor.
+	#endif
+
+	/* Set clock polarity */
+	#if CONFIG_SPI_CLOCK_POL == 1
+		SPCR |= BV(CPOL);
+	#endif
+
+	/* Set clock phase */
+	#if CONFIG_SPI_CLOCK_PHASE == 1
+		SPCR |= BV(CPHA);
+	#endif
 	SER_SPI_BUS_TXINIT;
 
 	SER_STROBE_INIT;
@@ -536,7 +606,7 @@ static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
 	SER_SPI_BUS_TXCLOSE;
 
 	/* Set all pins as inputs */
-	SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT));
+	ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
 }
 
 static void spi_starttx(struct SerialHardware *_hw)
@@ -657,7 +727,7 @@ static struct AvrSerial UARTDescs[SER_CNT] =
 	}
 };
 
-struct SerialHardware* ser_hw_getdesc(int unit)
+struct SerialHardware *ser_hw_getdesc(int unit)
 {
 	ASSERT(unit < SER_CNT);
 	return &UARTDescs[unit].hw;
@@ -670,7 +740,7 @@ struct SerialHardware* ser_hw_getdesc(int unit)
 
 #if CONFIG_SER_HWHANDSHAKE
 
-//! This interrupt is triggered when the CTS line goes high
+/// This interrupt is triggered when the CTS line goes high
 SIGNAL(SIG_CTS)
 {
 	// Re-enable UDR empty interrupt and TX, then disable CTS interrupt
@@ -681,7 +751,7 @@ SIGNAL(SIG_CTS)
 #endif // CONFIG_SER_HWHANDSHAKE
 
 
-/*!
+/**
  * Serial 0 TX interrupt handler
  */
 SIGNAL(SIG_UART0_DATA)
@@ -717,7 +787,7 @@ SIGNAL(SIG_UART0_DATA)
 }
 
 #ifdef SER_UART0_BUS_TXOFF
-/*!
+/**
  * Serial port 0 TX complete interrupt handler.
  *
  * This IRQ is usually disabled.  The UDR-empty interrupt
@@ -752,7 +822,7 @@ SIGNAL(SIG_UART0_TRANS)
 
 #if AVR_HAS_UART1
 
-/*!
+/**
  * Serial 1 TX interrupt handler
  */
 SIGNAL(SIG_UART1_DATA)
@@ -788,7 +858,7 @@ SIGNAL(SIG_UART1_DATA)
 }
 
 #ifdef SER_UART1_BUS_TXOFF
-/*!
+/**
  * Serial port 1 TX complete interrupt handler.
  *
  * \sa port 0 TX complete handler.
@@ -813,7 +883,7 @@ SIGNAL(SIG_UART1_TRANS)
 #endif // AVR_HAS_UART1
 
 
-/*!
+/**
  * Serial 0 RX complete interrupt handler.
  *
  * This handler is interruptible.
@@ -867,7 +937,7 @@ SIGNAL(SIG_UART0_RECV)
 
 #if AVR_HAS_UART1
 
-/*!
+/**
  * Serial 1 RX complete interrupt handler.
  *
  * This handler is interruptible.
@@ -916,7 +986,7 @@ SIGNAL(SIG_UART1_RECV)
 #endif // AVR_HAS_UART1
 
 
-/*!
+/**
  * SPI interrupt handler
  */
 SIGNAL(SIG_SPI)