X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=bertos%2Fcfg%2Fcfg_ser.h;h=e7d5cc43d9f179db1ec9d66d2fa1adcc27af6cbf;hb=3971934daffeaa21a6cc4f2b86e38714f7e092c8;hp=813328060ec1af41847094e238da3d318dbe76e6;hpb=505f66eae1b55bf337f8f765596121a10b5898c7;p=bertos.git

diff --git a/bertos/cfg/cfg_ser.h b/bertos/cfg/cfg_ser.h
index 81332806..e7d5cc43 100644
--- a/bertos/cfg/cfg_ser.h
+++ b/bertos/cfg/cfg_ser.h
@@ -32,8 +32,6 @@
  *
  * \brief Configuration file for serial module.
  *
- * \version $Id$
- *
  * \author Daniele Basile <asterix@develer.com>
  */
 
@@ -64,7 +62,7 @@
  * Size of the outbound FIFO buffer for port 1 [bytes].
  * $WIZ$ type = "int"
  * $WIZ$ min = 2
- * $WIZ$ supports = "at91 and not atmega8 and not atmega168 and not atmega32"
+ * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
  */
 #define CONFIG_UART1_TXBUFSIZE  32
 
@@ -72,10 +70,42 @@
  * Size of the inbound FIFO buffer for port 1 [bytes].
  * $WIZ$ type = "int"
  * $WIZ$ min = 2
- * $WIZ$ supports = "at91 and not atmega8 and not atmega168 and not atmega32"
+ * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
  */
 #define CONFIG_UART1_RXBUFSIZE  32
 
+/**
+ * Size of the outbound FIFO buffer for port 2 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2"
+ */
+#define CONFIG_UART2_TXBUFSIZE  32
+
+/**
+ * Size of the inbound FIFO buffer for port 2 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2"
+ */
+#define CONFIG_UART2_RXBUFSIZE  32
+
+/**
+ * Size of the outbound FIFO buffer for port 3 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lpc2"
+ */
+#define CONFIG_UART3_TXBUFSIZE  32
+
+/**
+ * Size of the inbound FIFO buffer for port 3 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lpc2"
+ */
+#define CONFIG_UART3_RXBUFSIZE  32
+
 
 /**
  * Size of the outbound FIFO buffer for SPI port [bytes].
@@ -130,14 +160,14 @@
  *
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_order_bit"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr and not xmega32d"
  */
 #define CONFIG_SPI_DATA_ORDER	SER_MSB_FIRST
 
 /**
  * SPI clock division factor.
  * $WIZ$ type = "int"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr and not xmega32d"
  */
 #define CONFIG_SPI_CLOCK_DIV	16
 
@@ -145,7 +175,7 @@
  * SPI clock polarity: normal low or normal high.
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_spi_pol"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr and not xmega32d"
  */
 #define CONFIG_SPI_CLOCK_POL        SPI_NORMAL_LOW
 
@@ -154,7 +184,7 @@
  * sample on second clock edge.
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_spi_phase"
- * $WIZ$ supports = "avr"
+ * $WIZ$ supports = "avr and not xmega32d"
  */
 #define CONFIG_SPI_CLOCK_PHASE	    SPI_SAMPLE_ON_FIRST_EDGE