X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=bertos%2Fcpu%2Farm%2Fdrv%2Fser_at91.c;h=a58c7dd9d1a52c5b49099fd491617110c3cffeb2;hb=bdcc52e5f18159cadc413c53dd14ef468a6de376;hp=74cca47bffdbdfd47949e0e9f60f95890d09d79a;hpb=345f93de1963f49bdb194d2b06c8c5d7ba0a3e5f;p=bertos.git diff --git a/bertos/cpu/arm/drv/ser_at91.c b/bertos/cpu/arm/drv/ser_at91.c index 74cca47b..a58c7dd9 100644 --- a/bertos/cpu/arm/drv/ser_at91.c +++ b/bertos/cpu/arm/drv/ser_at91.c @@ -38,19 +38,22 @@ * \author Daniele Basile */ +#include "hw/hw_ser.h" /* Required for bus macros overrides */ +#include "hw/hw_cpu.h" /* CLOCK_FREQ */ + +#include "cfg/cfg_ser.h" +#include + + #include #include + #include #include -#include /* Required for bus macros overrides */ -#include /* CLOCK_FREQ */ - #include -#include -#include #define SERIRQ_PRIORITY 4 ///< default priority for serial irqs. @@ -287,8 +290,8 @@ static void uart0_init( US0_IDR = 0xFFFFFFFF; /* Set the vector. */ AIC_SVR(US0_ID) = uart0_irq_dispatcher; - /* Initialize to edge triggered with defined priority. */ - AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; + /* Initialize to level sensitive with defined priority. */ + AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | SERIRQ_PRIORITY; PMC_PCER = BV(US0_ID); /* @@ -382,8 +385,8 @@ static void uart1_init( US1_IDR = 0xFFFFFFFF; /* Set the vector. */ AIC_SVR(US1_ID) = uart1_irq_dispatcher; - /* Initialize to edge triggered with defined priority. */ - AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; + /* Initialize to level sensitive with defined priority. */ + AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | SERIRQ_PRIORITY; PMC_PCER = BV(US1_ID); /* @@ -792,6 +795,7 @@ static void uart0_irq_rx(void) /* Should be read before US_CRS */ ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); + US0_CR = BV(US_RSTSTA); char c = US0_RHR; struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo; @@ -856,6 +860,7 @@ static void uart1_irq_rx(void) /* Should be read before US_CRS */ ser_uart1->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR); + US1_CR = BV(US_RSTSTA); char c = US1_RHR; struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;