X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=bertos%2Fcpu%2Favr%2Fdrv%2Fadc_avr.c;h=7e932f62ecd1e2d1751058c7450f735d1f68978c;hb=4208123bfbccd41e7c684fa5e5fb13f1e472fcf0;hp=942345a7466538e03a7c13a7a4b57896828afb8d;hpb=92d5e5f668bb596036e7c4fe674b29448f7ac65d;p=bertos.git

diff --git a/bertos/cpu/avr/drv/adc_avr.c b/bertos/cpu/avr/drv/adc_avr.c
index 942345a7..7e932f62 100644
--- a/bertos/cpu/avr/drv/adc_avr.c
+++ b/bertos/cpu/avr/drv/adc_avr.c
@@ -31,25 +31,40 @@
  *
  * \brief ADC hardware-specific definition
  *
- * \version $Id$
  * \author Francesco Sacchi <batt@develer.com>
+ *
+ * This module is automatically included so no need to include
+ * in test list.
+ * notest: avr
+ *
+ * $WIZ$
  */
 
 #include "adc_avr.h"
 
 #include "cfg/cfg_adc.h"
-#include "cfg/cfg_kern.h"
+#include "cfg/cfg_proc.h"
+#include "cfg/cfg_signal.h"
 #include <cfg/macros.h>
 #include <cfg/compiler.h>
 
+#include <cpu/irq.h> // IRQ_ASSERT_ENABLED()
+
 #include <drv/adc.h>
 
 #include <avr/io.h>
 #include <avr/interrupt.h>
 
+/**
+ * ADC voltage referencese.
+ *
+ * $WIZ$ avr_adc_refs = "ADC_AVR_AREF", "ADC_AVR_AVCC", "ADC_AVR_INT256"
+ * \{
+ */
 #define ADC_AVR_AREF   0
 #define ADC_AVR_AVCC   1
 #define ADC_AVR_INT256 2
+/* \} */
 
 #if CONFIG_KERN
 	#include <cfg/module.h>
@@ -58,7 +73,7 @@
 
 
 	#if !CONFIG_KERN_SIGNALS
-		#error Signals must be active to use ADC with kernel
+		#error Signals must be active to use the ADC with kernel
 	#endif
 
 	/* Signal adc convertion end */
@@ -73,7 +88,7 @@
 	 */
 	ISR(ADC_vect)
 	{
-		sig_signal(adc_process, SIG_ADC_COMPLETE);
+		sig_post(adc_process, SIG_ADC_COMPLETE);
 	}
 #endif /* CONFIG_KERN */
 
@@ -81,10 +96,16 @@
  * Select mux channel \a ch.
  * \todo only first 8 channels are selectable!
  */
-INLINE void adc_hw_select_ch(uint8_t ch)
+void adc_hw_select_ch(uint8_t ch)
 {
 	/* Set to 0 all mux registers */
-	ADMUX &= ~(BV(MUX3) | BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
+	#if CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA168
+		ADMUX &= ~(BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
+	#elif CPU_AVR_ATMEGA32 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
+		ADMUX &= ~(BV(MUX4) | BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
+	#else
+		#error Unknown CPU
+	#endif
 
 	/* Select channel, only first 8 channel modes are supported for now */
 	ADMUX |= (ch & 0x07);
@@ -96,7 +117,7 @@ INLINE void adc_hw_select_ch(uint8_t ch)
  * If a kernel is present, preempt until convertion is complete, otherwise
  * a busy wait on ADCS bit is done.
  */
-INLINE uint16_t adc_hw_read(void)
+uint16_t adc_hw_read(void)
 {
 	// Ensure another convertion is not running.
 	ASSERT(!(ADCSRA & BV(ADSC)));
@@ -106,7 +127,7 @@ INLINE uint16_t adc_hw_read(void)
 
 	#if CONFIG_KERN
 		// Ensure IRQs enabled.
-		ASSERT(IRQ_ENABLED());
+		IRQ_ASSERT_ENABLED();
 		adc_process = proc_current();
 		sig_wait(SIG_ADC_COMPLETE);
 	#else
@@ -120,7 +141,7 @@ INLINE uint16_t adc_hw_read(void)
 /**
  * Init ADC hardware.
  */
-INLINE void adc_hw_init(void)
+void adc_hw_init(void)
 {
 	/*
 	 * Select channel 0 as default,
@@ -141,8 +162,10 @@ INLINE void adc_hw_init(void)
 		#error Unsupported ADC ref value.
 	#endif
 
+	#if defined(ADCSRB)
 	/* Disable Auto trigger source: ADC in Free running mode. */
 	ADCSRB = 0;
+	#endif
 
 	/* Enable ADC, disable autotrigger mode. */
 	ADCSRA = BV(ADEN);