X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=bertos%2Fcpu%2Favr%2Fdrv%2Fser_avr.c;h=7f8cf932c2bd8f6cbd8d219d19988aa37a02cccc;hb=111bf6c8f1d9ef14df24586fa67500fdc997163c;hp=ee6c6ab10437052ebd977f57a32be1909ff419cd;hpb=75387a35a4ee559b62ac27cd871077428f82f88d;p=bertos.git

diff --git a/bertos/cpu/avr/drv/ser_avr.c b/bertos/cpu/avr/drv/ser_avr.c
index ee6c6ab1..7f8cf932 100644
--- a/bertos/cpu/avr/drv/ser_avr.c
+++ b/bertos/cpu/avr/drv/ser_avr.c
@@ -74,7 +74,7 @@
 	/*\}*/
 #endif
 
-#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
+#if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
 	#define BIT_RXCIE0 RXCIE0
 	#define BIT_RXEN0  RXEN0
 	#define BIT_TXEN0  TXEN0
@@ -84,7 +84,7 @@
 	#define BIT_RXEN1  RXEN1
 	#define BIT_TXEN1  TXEN1
 	#define BIT_UDRIE1 UDRIE1
-	#if CPU_AVR_ATMEGA1280
+	#if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
 		#define BIT_RXCIE2 RXCIE2
 		#define BIT_RXEN2  RXEN2
 		#define BIT_TXEN2  TXEN2
@@ -332,7 +332,7 @@
 
 /* SPI port and pin configuration */
 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281 \
-    || CPU_AVR_ATMEGA1280
+    || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
 	#define SPI_PORT      PORTB
 	#define SPI_DDR       DDRB
 	#define SPI_SS_BIT    PB0
@@ -355,12 +355,19 @@
 	#define SPI_SCK_BIT   PB5
 	#define SPI_MOSI_BIT  PB3
 	#define SPI_MISO_BIT  PB4
+#elif CPU_AVR_ATMEGA32
+	#define SPI_PORT      PORTB
+	#define SPI_DDR       DDRB
+	#define SPI_SS_BIT    PB4
+	#define SPI_SCK_BIT   PB7
+	#define SPI_MOSI_BIT  PB5
+	#define SPI_MISO_BIT  PB6
 #else
 	#error Unknown architecture
 #endif
 
 /* USART register definitions */
-#if CPU_AVR_ATMEGA1280
+#if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
 	#define AVR_HAS_UART1 1
 	#define AVR_HAS_UART2 1
 	#define AVR_HAS_UART3 1
@@ -375,7 +382,7 @@
 	#define USART0_UDRE_vect USART_UDRE_vect
 	#define USART0_RX_vect USART_RX_vect
 	#define USART0_TX_vect USART_TX_vect
-#elif CPU_AVR_ATMEGA8
+#elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA32
 	#define AVR_HAS_UART1 0
 	#define AVR_HAS_UART2 0
 	#define AVR_HAS_UART3 0
@@ -385,9 +392,11 @@
 	#define UDR0   UDR
 	#define UBRR0L UBRRL
 	#define UBRR0H UBRRH
+	#define UPM01  UPM1
+	#define UPM00  UPM0
 	#define USART0_UDRE_vect USART_UDRE_vect
-	#define USART0_RX_vect USART_RX_vect
-	#define USART0_TX_vect USART_TX_vect
+	#define USART0_RX_vect USART_RXC_vect
+	#define USART0_TX_vect USART_TXC_vect
 #elif CPU_AVR_ATMEGA103
 	#define AVR_HAS_UART1 0
 	#define AVR_HAS_UART2 0