X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=bertos%2Fcpu%2Favr%2Fdrv%2Fser_avr.c;h=c7c36ff77e163e83cde9fd0bc495b3d8309d89e3;hb=402db875d587a89e87e545883514dca50bc5ca54;hp=21da6b8eb2f6ea36f334f7e3ad60db9dfca6d67d;hpb=e62ca0b357f09804d7d894949df44224c9d74bb7;p=bertos.git diff --git a/bertos/cpu/avr/drv/ser_avr.c b/bertos/cpu/avr/drv/ser_avr.c index 21da6b8e..c7c36ff7 100644 --- a/bertos/cpu/avr/drv/ser_avr.c +++ b/bertos/cpu/avr/drv/ser_avr.c @@ -26,7 +26,7 @@ * invalidate any other reasons why the executable file might be covered by * the GNU General Public License. * - * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/) + * Copyright 2003, 2004, 2010 Develer S.r.l. (http://www.develer.com/) * Copyright 2000 Bernie Innocenti * * --> @@ -37,15 +37,17 @@ * * \author Bernie Innocenti * \author Stefano Fedrigo + * \author Luca Ottaviano */ #include "hw/hw_ser.h" /* Required for bus macros overrides */ -#include "hw/hw_cpu.h" /* CLOCK_FREQ */ +#include /* CPU_FREQ */ #include "cfg/cfg_ser.h" #include /* DIV_ROUND */ #include +#include // ARCH_NIGHTTEST #include #include @@ -84,6 +86,16 @@ #define BIT_RXEN1 RXEN1 #define BIT_TXEN1 TXEN1 #define BIT_UDRIE1 UDRIE1 +#elif CPU_AVR_ATMEGA328P + #define BIT_RXCIE0 RXCIE0 + #define BIT_RXEN0 RXEN0 + #define BIT_TXEN0 TXEN0 + #define BIT_UDRIE0 UDRIE0 + + #define BIT_RXCIE1 RXCIE0 + #define BIT_RXEN1 RXEN0 + #define BIT_TXEN1 TXEN0 + #define BIT_UDRIE1 UDRIE0 #else #define BIT_RXCIE0 RXCIE #define BIT_RXEN0 RXEN @@ -247,7 +259,16 @@ #define SPI_SCK_BIT PB1 #define SPI_MOSI_BIT PB2 #define SPI_MISO_BIT PB3 -#elif CPU_AVR_ATMEGA8 +// TODO: these bits are the same as ATMEGA8 but the defines in avr-gcc are different. +// They should be the same! +#elif CPU_AVR_ATMEGA328P + #define SPI_PORT PORTB + #define SPI_DDR DDRB + #define SPI_SS_BIT PORTB2 + #define SPI_SCK_BIT PORTB5 + #define SPI_MOSI_BIT PORTB3 + #define SPI_MISO_BIT PORTB4 +#elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA168 #define SPI_PORT PORTB #define SPI_DDR DDRB #define SPI_SS_BIT PB2 @@ -261,6 +282,11 @@ /* USART register definitions */ #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281 #define AVR_HAS_UART1 1 +#elif CPU_AVR_ATMEGA328P + #define AVR_HAS_UART1 0 + #define USART0_UDRE_vect USART_UDRE_vect + #define USART0_RX_vect USART_RX_vect + #define SIG_UART0_TRANS SIG_UART_TRANS #elif CPU_AVR_ATMEGA8 #define AVR_HAS_UART1 0 #define UCSR0A UCSRA @@ -269,6 +295,7 @@ #define UDR0 UDR #define UBRR0L UBRRL #define UBRR0H UBRRH +/* TODO: The following SIGs are old style interrupts, must be refactored */ #define SIG_UART0_DATA SIG_UART_DATA #define SIG_UART0_RECV SIG_UART_RECV #define SIG_UART0_TRANS SIG_UART_TRANS @@ -278,6 +305,7 @@ #define UDR0 UDR #define UCSR0A USR #define UBRR0L UBRR +/* TODO: The following SIGs are old style interrupts, must be refactored */ #define SIG_UART0_DATA SIG_UART_DATA #define SIG_UART0_RECV SIG_UART_RECV #define SIG_UART0_TRANS SIG_UART_TRANS @@ -286,23 +314,6 @@ #endif -/** - * \def CONFIG_SER_STROBE - * - * This is a debug facility that can be used to - * monitor SER interrupt activity on an external pin. - * - * To use strobes, redefine the macros SER_STROBE_ON, - * SER_STROBE_OFF and SER_STROBE_INIT and set - * CONFIG_SER_STROBE to 1. - */ -#if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE - #define SER_STROBE_ON do {/*nop*/} while(0) - #define SER_STROBE_OFF do {/*nop*/} while(0) - #define SER_STROBE_INIT do {/*nop*/} while(0) -#endif - - /* From the high-level serial driver */ extern struct Serial *ser_handles[SER_CNT]; @@ -377,7 +388,7 @@ static void uart0_enabletxirq(struct SerialHardware *_hw) static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate) { /* Compute baud-rate period */ - uint16_t period = DIV_ROUND(CLOCK_FREQ / 16UL, rate) - 1; + uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1; #if !CPU_AVR_ATMEGA103 UBRR0H = (period) >> 8; @@ -430,7 +441,7 @@ static void uart1_enabletxirq(struct SerialHardware *_hw) static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate) { /* Compute baud-rate period */ - uint16_t period = DIV_ROUND(CLOCK_FREQ / 16UL, rate) - 1; + uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1; UBRR1H = (period) >> 8; UBRR1L = (period); @@ -470,7 +481,7 @@ static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct * - as input but tied high forever! * This driver set the pin as output. */ - #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts. + #warning FIXME:SPI SS pin set as output for proper operation, check schematics for possible conflicts. ATOMIC(SPI_DDR |= BV(SPI_SS_BIT)); ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT)); @@ -661,10 +672,10 @@ struct SerialHardware *ser_hw_getdesc(int unit) #if CONFIG_SER_HWHANDSHAKE /// This interrupt is triggered when the CTS line goes high -SIGNAL(SIG_CTS) +DECLARE_ISR(SIG_CTS) { // Re-enable UDR empty interrupt and TX, then disable CTS interrupt - UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); + UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); EIMSK &= ~EIMSKF_CTS; } @@ -674,7 +685,7 @@ SIGNAL(SIG_CTS) /** * Serial 0 TX interrupt handler */ -SIGNAL(USART0_UDRE_vect) +DECLARE_ISR(USART0_UDRE_vect) { SER_STROBE_ON; @@ -692,7 +703,7 @@ SIGNAL(USART0_UDRE_vect) { // Disable rx interrupt and tx, enable CTS interrupt // UNTESTED - UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN); + UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); EIFR |= EIMSKF_CTS; EIMSK |= EIMSKF_CTS; } @@ -722,7 +733,7 @@ SIGNAL(USART0_UDRE_vect) * otherwise we'd stop the serial port with some data * still pending in the buffer. */ -SIGNAL(SIG_UART0_TRANS) +DECLARE_ISR(SIG_UART0_TRANS) { SER_STROBE_ON; @@ -733,7 +744,7 @@ SIGNAL(SIG_UART0_TRANS) UARTDescs[SER_UART0].sending = false; } else - UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); + UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); SER_STROBE_OFF; } @@ -745,7 +756,7 @@ SIGNAL(SIG_UART0_TRANS) /** * Serial 1 TX interrupt handler */ -SIGNAL(USART1_UDRE_vect) +DECLARE_ISR(USART1_UDRE_vect) { SER_STROBE_ON; @@ -763,7 +774,7 @@ SIGNAL(USART1_UDRE_vect) { // Disable rx interrupt and tx, enable CTS interrupt // UNTESTED - UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN); + UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); EIFR |= EIMSKF_CTS; EIMSK |= EIMSKF_CTS; } @@ -783,7 +794,7 @@ SIGNAL(USART1_UDRE_vect) * * \sa port 0 TX complete handler. */ -SIGNAL(SIG_UART1_TRANS) +DECLARE_ISR(USART1_TX_vect) { SER_STROBE_ON; @@ -794,7 +805,7 @@ SIGNAL(SIG_UART1_TRANS) UARTDescs[SER_UART1].sending = false; } else - UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN); + UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); SER_STROBE_OFF; } @@ -818,7 +829,7 @@ SIGNAL(SIG_UART1_TRANS) * RXCIE is cleared. Unfortunately the RXC flag is read-only * and can't be cleared by code. */ -SIGNAL(USART0_RX_vect) +DECLARE_ISR(USART0_RX_vect) { SER_STROBE_ON; @@ -866,9 +877,9 @@ SIGNAL(USART0_RX_vect) * is heavily loaded, because an interrupt could be retriggered * when executing the handler prologue before RXCIE is disabled. * - * \see SIGNAL(USART1_RX_vect) + * \see DECLARE_ISR(USART1_RX_vect) */ -SIGNAL(USART1_RX_vect) +DECLARE_ISR(USART1_RX_vect) { SER_STROBE_ON; @@ -909,7 +920,7 @@ SIGNAL(USART1_RX_vect) /** * SPI interrupt handler */ -SIGNAL(SIG_SPI) +DECLARE_ISR(SIG_SPI) { SER_STROBE_ON;