X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fclock_sam3.c;h=38b526269903aa2c3cf65aa56ae958d8d9c5f0d8;hb=f24ae17a2dcab5997de211f66fcec0a6e446bb84;hp=fbc79062216a4ad8207e23423412e65a1aa91860;hpb=d83ff60c86ab9c3fae79eddc491adebd15959e1d;p=bertos.git diff --git a/bertos/cpu/cortex-m3/drv/clock_sam3.c b/bertos/cpu/cortex-m3/drv/clock_sam3.c index fbc79062..38b52626 100644 --- a/bertos/cpu/cortex-m3/drv/clock_sam3.c +++ b/bertos/cpu/cortex-m3/drv/clock_sam3.c @@ -30,18 +30,27 @@ * * --> * - * \brief AT91SAM3 clocking driver. + * \brief Atmel SAM3 clock setup. * * \author Stefano Fedrigo */ #include "clock_sam3.h" -#include #include #include +#include + + +/* Frequency of board main oscillator */ +// TODO: wizard config +#define BOARDOSC_FREQ 12000000 + +/* Main crystal oscillator startup time, optimal value for CPU_FREQ == 48 MHz */ +#define BOARD_OSC_COUNT (CKGR_MOR_MOSCXTST(0x8)) + +/* Timer countdown timeout for clock initialization operations */ +#define CLOCK_TIMEOUT 0xFFFFFFFF -/* Value to use when writing CKGR_MOR, to unlock write */ -#define CKGR_KEY 0x37 /* * Try to evaluate the correct divider and multiplier value depending @@ -63,8 +72,7 @@ INLINE uint32_t evaluate_pll(void) { for (div = 1; div <= 24; div++) { - // RC oscillator set to 12 MHz - freq = 12000000 / div * (1 + mul); + freq = BOARDOSC_FREQ / div * (1 + mul); if (ABS((int)CPU_FREQ - freq) < best_delta) { best_delta = ABS((int)CPU_FREQ - freq); best_mul = mul; @@ -73,21 +81,69 @@ INLINE uint32_t evaluate_pll(void) } } - // Bit 29 must always be set to 1 - return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul) | BV(29); + return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul); } void clock_init(void) { - /* Enable and configure internal Fast RC oscillator */ - CKGR_MOR_R = - CKGR_MOR_KEY(CKGR_KEY) // Unlock key - | CKGR_MOR_MOSCRCEN // Main On-Chip RC oscillator enable - | CKGR_MOR_MOSCRCF_12MHZ; // RC oscillator frequency + uint32_t timeout; + + /* Disable watchdog */ + WDT_MR = BV(WDT_WDDIS); + +#if CPU_CM3_SAM3X + /* Set wait states for flash access, needed for higher CPU clock rates */ + EEFC0_FMR = EEFC_FMR_FWS(2); + EEFC1_FMR = EEFC_FMR_FWS(2); +#else + EEFC0_FMR = EEFC_FMR_FWS(3); + + // TODO: check if this is needed in sam3n-ek too, very slow start-up + // Select external slow clock + if (!(SUPC_SR & BV(SUPC_SR_OSCSEL))) + { + SUPC_CR = BV(SUPC_CR_XTALSEL) | SUPC_CR_KEY(0xA5); + while (!(SUPC_SR & BV(SUPC_SR_OSCSEL))); + } +#endif + + // Initialize main oscillator + if (!(CKGR_MOR & BV(CKGR_MOR_MOSCSEL))) + { + CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN); + timeout = CLOCK_TIMEOUT; + while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout); + } + + // Switch to external oscillator + CKGR_MOR = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN) | BV(CKGR_MOR_MOSCSEL); + timeout = CLOCK_TIMEOUT; + while (!(PMC_SR & BV(PMC_SR_MOSCSELS)) && --timeout); + + PMC_MCKR = (PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_MASK) | PMC_MCKR_CSS_MAIN_CLK; + timeout = CLOCK_TIMEOUT; + while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout); + + // Initialize and enable PLL clock + CKGR_PLLR = evaluate_pll() | BV(CKGR_PLLR_STUCKTO1) | CKGR_PLLR_PLLCOUNT(0x1); + timeout = CLOCK_TIMEOUT; + while (!(PMC_SR & BV(PMC_SR_LOCK)) && --timeout); + + PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK; + timeout = CLOCK_TIMEOUT; + while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout); - /* Master clock: select PLL clock and no prescaling */ - PMC_MCKR_R = PMC_MCKR_CSS_PLL_CLK; + PMC_MCKR = PMC_MCKR_CSS_PLL_CLK; + timeout = CLOCK_TIMEOUT; + while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout); - CKGR_PLLR_R = evaluate_pll(); + /* Enable clock on PIO for inputs */ + // TODO: move this in gpio_init() for better power management? +#if CPU_CM3_SAM3X + PMC_PCER = BV(PIOA_ID) | BV(PIOB_ID) | BV(PIOC_ID) + | BV(PIOD_ID) | BV(PIOE_ID) | BV(PIOF_ID); +#else + PMC_PCER = BV(PIOA_ID) | BV(PIOB_ID) | BV(PIOC_ID); +#endif }