X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fi2s_sam3.c;h=bfd579345b3009ede25c7229c3f890e4c83b54da;hb=563795df4180aaceb7d69306551230c98fbca879;hp=8a35c58166d7f9c38c15d7a30dd87bba88cc46b7;hpb=d828b90743ba303ae954220ffa968990dfff5963;p=bertos.git diff --git a/bertos/cpu/cortex-m3/drv/i2s_sam3.c b/bertos/cpu/cortex-m3/drv/i2s_sam3.c index 8a35c581..bfd57934 100644 --- a/bertos/cpu/cortex-m3/drv/i2s_sam3.c +++ b/bertos/cpu/cortex-m3/drv/i2s_sam3.c @@ -35,11 +35,9 @@ */ -/* - * TODO: Revise the public api of this module to be more generic. Evalutate to - * implement the more generic layer to be common to all I2S BeRTOS drivers. - */ -#include "i2s_sam3.h" + +#include "hw/hw_i2s.h" + #include "cfg/cfg_i2s.h" // Define log settings for cfg/log.h. @@ -48,135 +46,453 @@ #include #include -#include +#include +#include + +#include #include #include -#define DATALEN (15 & SSC_DATLEN_MASK) -// FIXME: this is not correct for 16 <= DATALEN < 24 -#define PDC_DIV ((DATALEN / 8) + 1) -/* - * PDC_DIV must be 1, 2 or 4, which are the bytes that are transferred - * each time the PDC reads from memory. - */ -STATIC_ASSERT(PDC_DIV % 2 == 0); -#define PDC_COUNT (CONFIG_PLAY_BUF_LEN / PDC_DIV) +#include + + +#define I2S_DMAC_CH 0 +#define I2S_CACHED_CHUNK_SIZE 2 + + +#define I2S_TX_DMAC_CFG (BV(DMAC_CFG_DST_H2SEL) | \ + BV(DMAC_CFG_SOD) | \ + ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \ + (4 & DMAC_CFG_SRC_PER_MASK)) + +#define I2S_TX_DMAC_CTRLB (DMAC_CTRLB_FC_MEM2PER_DMA_FC | \ + DMAC_CTRLB_DST_INCR_FIXED | \ + DMAC_CTRLB_SRC_INCR_INCREMENTING) + + +#define I2S_RX_DMAC_CFG (BV(DMAC_CFG_SRC_H2SEL) | \ + BV(DMAC_CFG_SOD) | \ + ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \ + (4 & DMAC_CFG_SRC_PER_MASK)) + +#define I2S_RX_DMAC_CTRLB (DMAC_CTRLB_FC_PER2MEM_DMA_FC | \ + DMAC_CTRLB_DST_INCR_INCREMENTING | \ + DMAC_CTRLB_SRC_INCR_FIXED) + + +#if CONFIG_WORD_BIT_SIZE == 32 + #define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \ + DMAC_CTRLA_DST_WIDTH_WORD) + #define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \ + DMAC_CTRLA_DST_WIDTH_WORD) + #define I2S_WORD_BYTE_SIZE 4 +#elif CONFIG_WORD_BIT_SIZE == 16 + + #define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \ + DMAC_CTRLA_DST_WIDTH_HALF_WORD) + #define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \ + DMAC_CTRLA_DST_WIDTH_HALF_WORD) + #define I2S_WORD_BYTE_SIZE 2 + +#elif CONFIG_WORD_BIT_SIZE == 8 + + #define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_BYTE | \ + DMAC_CTRLA_DST_WIDTH_BYTE) + #define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_BYTE | \ + DMAC_CTRLA_DST_WIDTH_BYTE) + #define I2S_WORD_BYTE_SIZE 1 + +#else + #error Wrong i2s word size. +#endif + + +#define I2S_STATUS_ERR BV(0) +#define I2S_STATUS_SINGLE_TRASF BV(1) +#define I2S_STATUS_TX BV(2) +#define I2S_STATUS_END_TX BV(3) +#define I2S_STATUS_RX BV(4) +#define I2S_STATUS_END_RX BV(5) + + +static Event data_ready; + +DmacDesc lli0; +DmacDesc lli1; +DmacDesc *curr; +DmacDesc *next; +DmacDesc *prev; + +static uint8_t i2s_status; +static uint8_t *sample_buff; +static size_t next_idx = 0; +static size_t chunk_size = 0; +static size_t transfer_size = 0; + +static void sam3_i2s_txStop(I2s *i2s) +{ + (void)i2s; + SSC_CR = BV(SSC_TXDIS); + dmac_stop(I2S_DMAC_CH); -static uint8_t play_buf1[CONFIG_PLAY_BUF_LEN]; -static uint8_t play_buf2[CONFIG_PLAY_BUF_LEN]; + next_idx = 0; + transfer_size = 0; -// the buffer in PDC next is play_buf2 -volatile bool is_second_buf_next; + i2s_status |= I2S_STATUS_END_TX; + i2s_status &= ~I2S_STATUS_TX; + event_do(&data_ready); +} -uint8_t *i2s_getBuffer(unsigned buf_num) +static void sam3_i2s_txWait(I2s *i2s) { - LOG_INFO("getBuffer start\n"); + (void)i2s; + event_wait(&data_ready); +} - if (i2s_isPlaying()) +static void i2s_dmac_irq(uint32_t status) +{ + if (i2s_status & I2S_STATUS_SINGLE_TRASF) { - ASSERT(0); - return 0; + i2s_status &= ~I2S_STATUS_SINGLE_TRASF; } - - if (buf_num == I2S_SECOND_BUF) - return play_buf2; - else if (buf_num == I2S_FIRST_BUF) - return play_buf1; else - return 0; + { + if (status & (BV(I2S_DMAC_CH) << DMAC_EBCIDR_ERR0)) + { + i2s_status |= I2S_STATUS_ERR; + // Disable to reset channel and clear fifo + dmac_stop(I2S_DMAC_CH); + } + else + { + prev = curr; + curr = next; + next = prev; + + if (i2s_status & I2S_STATUS_TX) + { + curr->src_addr = (uint32_t)&sample_buff[next_idx]; + curr->dst_addr = (uint32_t)&SSC_THR; + curr->dsc_addr = (uint32_t)next; + curr->ctrla = I2S_TX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff); + curr->ctrlb = I2S_TX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN); + } + else + { + curr->src_addr = (uint32_t)&SSC_RHR; + curr->dst_addr = (uint32_t)&sample_buff[next_idx]; + curr->dsc_addr = (uint32_t)next; + curr->ctrla = I2S_RX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff); + curr->ctrlb = I2S_RX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN); + } + + } + } + event_do(&data_ready); } -uint8_t *i2s_getFreeBuffer(void) + +static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len) { - // wait PDC transmission end - if (!(SSC_SR & BV(SSC_ENDTX))) - return 0; + ASSERT(buf); + ASSERT(len >= slice_len); + ASSERT(!(len % slice_len)); + + i2s_status &= ~(I2S_STATUS_END_TX | I2S_STATUS_SINGLE_TRASF); + + sample_buff = (uint8_t *)buf; + next_idx = 0; + chunk_size = slice_len; + size_t remaing_size = len; + transfer_size = len; + + + memset(&lli0, 0, sizeof(DmacDesc)); + memset(&lli1, 0, sizeof(DmacDesc)); - uint8_t *ret_buf = 0; - // the last time we got called, the second buffer was in PDC next - if (is_second_buf_next) + prev = 0; + curr = &lli1; + next = &lli0; + + for (int i = 0; i < I2S_CACHED_CHUNK_SIZE; i++) { - is_second_buf_next = false; - ret_buf = play_buf1; + prev = curr; + curr = next; + next = prev; + + i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size); + + curr->src_addr = (uint32_t)&sample_buff[next_idx]; + curr->dst_addr = (uint32_t)&SSC_THR; + curr->dsc_addr = (uint32_t)next; + curr->ctrla = I2S_TX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff); + curr->ctrlb = I2S_TX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN); + + remaing_size -= chunk_size; + next_idx += chunk_size; + + if (remaing_size <= 0) + { + remaing_size = transfer_size; + next_idx = 0; + } } - // the last time the first buffer was in PDC next - else + + dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_TX_DMAC_CFG); + + if (dmac_start(I2S_DMAC_CH) < 0) { - is_second_buf_next = true; - ret_buf = play_buf2; + LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH)); + return; } - if (ret_buf) + i2s_status &= ~I2S_STATUS_ERR; + i2s_status |= I2S_STATUS_TX; + + SSC_CR = BV(SSC_TXEN); + + while (1) { - SSC_TNPR = (reg32_t) ret_buf; - SSC_TNCR = PDC_COUNT; + event_wait(&data_ready); + I2S_STROBE_ON(); + remaing_size -= chunk_size; + next_idx += chunk_size; + + if (remaing_size <= 0) + { + remaing_size = transfer_size; + next_idx = 0; + } + + if (i2s_status & I2S_STATUS_ERR) + { + LOG_ERR("Error while streaming.\n"); + break; + } + + if (i2s_status & I2S_STATUS_END_TX) + { + LOG_INFO("Stop streaming.\n"); + break; + } + + i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size); + I2S_STROBE_OFF(); } - return ret_buf; } -void i2s_stop(void) +static void sam3_i2s_rxStop(I2s *i2s) { - SSC_CR = BV(SSC_TXDIS); + (void)i2s; + SSC_CR = BV(SSC_RXDIS) | BV(SSC_TXDIS); + dmac_stop(I2S_DMAC_CH); + + i2s_status |= I2S_STATUS_END_RX; + next_idx = 0; + transfer_size = 0; + + i2s_status &= ~I2S_STATUS_RX; + + event_do(&data_ready); +} + +static void sam3_i2s_rxWait(I2s *i2s) +{ + (void)i2s; + event_wait(&data_ready); +} + +static void sam3_i2s_rxStart(I2s *i2s, void *buf, size_t len, size_t slice_len) +{ + ASSERT(buf); + ASSERT(len >= slice_len); + ASSERT(!(len % slice_len)); + + i2s_status &= ~(I2S_STATUS_END_RX | I2S_STATUS_SINGLE_TRASF); + + sample_buff = (uint8_t *)buf; + next_idx = 0; + chunk_size = slice_len; + size_t remaing_size = len; + transfer_size = len; + + memset(&lli0, 0, sizeof(DmacDesc)); + memset(&lli1, 0, sizeof(DmacDesc)); + + prev = 0; + curr = &lli1; + next = &lli0; + + for (int i = 0; i < I2S_CACHED_CHUNK_SIZE; i++) + { + prev = curr; + curr = next; + next = prev; + + curr->src_addr = (uint32_t)&SSC_RHR; + curr->dst_addr = (uint32_t)&sample_buff[next_idx]; + curr->dsc_addr = (uint32_t)next; + curr->ctrla = I2S_RX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff); + curr->ctrlb = I2S_RX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN); + + remaing_size -= chunk_size; + next_idx += chunk_size; + + if (remaing_size <= 0) + { + remaing_size = transfer_size; + next_idx = 0; + } + } + + dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_RX_DMAC_CFG); + + if (dmac_start(I2S_DMAC_CH) < 0) + { + LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH)); + return; + } + + i2s_status &= ~I2S_STATUS_ERR; + i2s_status |= I2S_STATUS_RX; + + SSC_CR = BV(SSC_TXEN) | BV(SSC_RXEN); + + while (1) + { + event_wait(&data_ready); + I2S_STROBE_ON(); + i2s->ctx.rx_callback(i2s, &sample_buff[next_idx], chunk_size); + + remaing_size -= chunk_size; + next_idx += chunk_size; + + if (remaing_size <= 0) + { + remaing_size = transfer_size; + next_idx = 0; + } + + if (i2s_status & I2S_STATUS_ERR) + { + LOG_ERR("Error while streaming.\n"); + break; + } + + if (i2s_status & I2S_STATUS_END_RX) + { + LOG_INFO("Stop streaming.\n"); + break; + } + I2S_STROBE_OFF(); + } } -bool i2s_start(void) +static bool sam3_i2s_isTxFinish(struct I2s *i2s) { - /* Some time must pass between disabling and enabling again the transmission - * on SSC. A good empirical value seems >15 us. We try to avoid putting an - * explicit delay, instead we disable the transmitter when a sound finishes - * and hope that the delay has passed before we enter here again. - */ - SSC_CR = BV(SSC_TXDIS); - timer_delay(10); + (void)i2s; + return (i2s_status & I2S_STATUS_END_TX); +} + +static bool sam3_i2s_isRxFinish(struct I2s *i2s) +{ + (void)i2s; + return (i2s_status & I2S_STATUS_END_RX); +} - SSC_PTCR = BV(PDC_PTCR_TXTDIS); - SSC_TPR = (reg32_t)play_buf1; - SSC_TCR = PDC_COUNT; - SSC_TNPR = (reg32_t)play_buf2; - SSC_TNCR = PDC_COUNT; - is_second_buf_next = true; +static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len) +{ + (void)i2s; + i2s_status |= I2S_STATUS_SINGLE_TRASF; - SSC_PTCR = BV(PDC_PTSR_TXTEN); + dmac_setSources(I2S_DMAC_CH, (uint32_t)buf, (uint32_t)&SSC_THR); + dmac_configureDmac(I2S_DMAC_CH, len / I2S_WORD_BYTE_SIZE, I2S_TX_DMAC_CFG, I2S_TX_DMAC_CTRLA, I2S_TX_DMAC_CTRLB); + dmac_start(I2S_DMAC_CH); - /* enable output */ SSC_CR = BV(SSC_TXEN); - - return true; } -#define BITS_PER_CHANNEL 16 -#define N_OF_CHANNEL 2 -// TODO: check the computed value? -/* The last parameter (2) is due to the hadware on at91sam7s. */ -#define MCK_DIV (CPU_FREQ / CONFIG_SAMPLE_FREQ / BITS_PER_CHANNEL / N_OF_CHANNEL / 2) +static void sam3_i2s_rxBuf(struct I2s *i2s, void *buf, size_t len) +{ + (void)i2s; -#define CONFIG_DELAY 1 -#define CONFIG_PERIOD 15 -#define CONFIG_DATNB 1 -#define CONFIG_FSLEN 15 + i2s_status |= I2S_STATUS_SINGLE_TRASF; -#define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK) -#define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK) -#define DATNB ((CONFIG_DATNB << SSC_DATNB_SHIFT) & SSC_DATNB_MASK) -#define FSLEN ((CONFIG_FSLEN << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK) + dmac_setSources(I2S_DMAC_CH, (uint32_t)&SSC_RHR, (uint32_t)buf); + dmac_configureDmac(I2S_DMAC_CH, len / I2S_WORD_BYTE_SIZE, I2S_RX_DMAC_CFG, I2S_RX_DMAC_CTRLA, I2S_RX_DMAC_CTRLB); + dmac_start(I2S_DMAC_CH); -#define SSC_DMA_IRQ_PRIORITY 5 + SSC_CR = BV(SSC_TXEN) | BV(SSC_RXEN); +} +static int sam3_i2s_write(struct I2s *i2s, uint32_t sample) +{ + (void)i2s; + + SSC_CR = BV(SSC_TXEN); + while(!(SSC_SR & BV(SSC_TXRDY))) + cpu_relax(); -static DECLARE_ISR(irq_ssc) + SSC_THR = sample; + return 0; +} + +static uint32_t sam3_i2s_read(struct I2s *i2s) { + (void)i2s; + + SSC_CR = BV(SSC_RXEN); + while(!(SSC_SR & BV(SSC_RXRDY))) + cpu_relax(); + + return SSC_RHR; } -void i2s_init(void) + +/* We divite for 2 because the min clock for i2s i MCLK/2 */ +#define MCK_DIV (CPU_FREQ / (CONFIG_SAMPLE_FREQ * CONFIG_WORD_BIT_SIZE * CONFIG_CHANNEL_NUM * 2)) +#define DATALEN ((CONFIG_WORD_BIT_SIZE - 1) & SSC_DATLEN_MASK) +#define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK) +#define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK) +#define DATNB ((CONFIG_WORD_PER_FRAME << SSC_DATNB_SHIFT) & SSC_DATNB_MASK) +#define FSLEN ((CONFIG_FRAME_SYNC_SIZE << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK) +#define EXTRA_FSLEN (CONFIG_EXTRA_FRAME_SYNC_SIZE << SSC_FSLEN_EXT) + +void i2s_init(I2s *i2s, int channel) { - SSC_PIO_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD); - PIO_PERIPH_SEL(SSC_PORT, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), SSC_TRAN_PERIPH); + (void)channel; + i2s->ctx.write = sam3_i2s_write; + i2s->ctx.tx_buf = sam3_i2s_txBuf; + i2s->ctx.tx_isFinish = sam3_i2s_isTxFinish; + i2s->ctx.tx_start = sam3_i2s_txStart; + i2s->ctx.tx_wait = sam3_i2s_txWait; + i2s->ctx.tx_stop = sam3_i2s_txStop; + + i2s->ctx.read = sam3_i2s_read; + i2s->ctx.rx_buf = sam3_i2s_rxBuf; + i2s->ctx.rx_isFinish = sam3_i2s_isRxFinish; + i2s->ctx.rx_start = sam3_i2s_rxStart; + i2s->ctx.rx_wait = sam3_i2s_rxWait; + i2s->ctx.rx_stop = sam3_i2s_rxStop; + + DB(i2s->ctx._type = I2S_SAM3X;) + + I2S_STROBE_INIT(); + + PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD); + PIO_PERIPH_SEL(PIOA_BASE, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), PIO_PERIPH_B); + + PIOB_PDR = BV(SSC_RD) | BV(SSC_RF); + PIO_PERIPH_SEL(PIOB_BASE, BV(SSC_RD) | BV(SSC_RF), PIO_PERIPH_A); + + /* clock the ssc */ + pmc_periphEnable(SSC_ID); /* reset device */ - SSC_CR = BV(SSC_SWRST); + SSC_CR = BV(SSC_SWRST) | BV(SSC_TXDIS) | BV(SSC_RXDIS); /* Set transmission clock */ SSC_CMR = MCK_DIV & SSC_DIV_MASK; @@ -188,7 +504,7 @@ void i2s_init(void) * - generate frame sync each 2*(PERIOD + 1) tramit clock * - Receive start on falling edge RF */ - SSC_TCMR = SSC_CKS_DIV | SSC_CKO_TRAN | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F; + SSC_TCMR = SSC_CKS_DIV | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_FALL_F; /* Set the transmission frame mode: * - data len DATALEN + 1 * - word per frame DATNB + 1 @@ -197,14 +513,16 @@ void i2s_init(void) * - MSB * - Frame sync output selection negative */ - SSC_TFMR = DATALEN | DATNB | FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE; + SSC_TFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE; - SSC_IDR = 0xFFFFFFFF; - sysirq_setHandler(INT_SSC, irq_ssc); - /* Clock DAC peripheral */ - pmc_periphEnable(SSC_ID); + // Receiver should start on TX and take the clock from TK + SSC_RCMR = SSC_CKS_CLK | BV(SSC_CKI) | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_TX; + SSC_RFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE; - /* Enable SSC */ - SSC_CR = BV(SSC_TXEN); + + SSC_IDR = 0xFFFFFFFF; + + dmac_enableCh(I2S_DMAC_CH, i2s_dmac_irq); + event_initGeneric(&data_ready); }