X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=bertos%2Fcpu%2Fcortex-m3%2Fdrv%2Fkdebug_lm3s.c;h=568920ecc713d77926413c187a880693e0dae2d1;hb=7b5a8ebc799a5d9486db4c2d89670b7ac7a236b4;hp=65c1dccb46512e36ccc917ee349840dccf6355a7;hpb=7d62f20a0d0dd38aa03997583c69bbc085896308;p=bertos.git

diff --git a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
index 65c1dccb..568920ec 100644
--- a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
@@ -39,74 +39,34 @@
 #include <cfg/macros.h> /* for BV() */
 #include <drv/clock_lm3s.h> /* lm3s_busyWait() */
 #include <drv/gpio_lm3s.h>
-#include <io/lm3s.h>
+#include <drv/ser_lm3s.h>
 #include "kdebug_lm3s.h"
 
-INLINE void uart_disable(size_t base)
-{
-	/* Disable the FIFO */
-	HWREG(base + UART_O_LCRH) &= ~UART_LCRH_FEN;
-	/* Disable the UART */
-	HWREG(base + UART_O_CTL) &=
-		~(UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE);
-}
-
-INLINE void uart_enable(size_t base)
-{
-	/* Enable the FIFO */
-	HWREG(base + UART_O_LCRH) |= UART_LCRH_FEN;
-	/* Enable RX, TX, and the UART */
-	HWREG(base + UART_O_CTL) |=
-			UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE;
-}
-
-INLINE void uart_config(size_t base, uint32_t baud, reg32_t config)
-{
-	unsigned long div;
-	bool hi_speed;
-
-	if (baud * 16 > CPU_FREQ)
-	{
-		hi_speed = true;
-		baud /= 2;
-	}
-	div = (CPU_FREQ * 8 / baud + 1) / 2;
-
-	uart_disable(base);
-
-	if (hi_speed)
-		HWREG(base + UART_O_CTL) |= UART_CTL_HSE;
-	else
-		HWREG(base + UART_O_CTL) &= ~UART_CTL_HSE;
-
-	/* Set the baud rate */
-	HWREG(base + UART_O_IBRD) = div / 64;
-	HWREG(base + UART_O_FBRD) = div % 64;
-
-	/* Set parity, data length, and number of stop bits. */
-	HWREG(base + UART_O_LCRH) = config;
-
-	/* Clear the flags register */
-	HWREG(base + UART_O_FR) = 0;
-
-	uart_enable(base);
-}
+#if CONFIG_KDEBUG_PORT == KDEBUG_PORT_DBGU
 
-INLINE bool uart_putchar(size_t base, unsigned char ch)
-{
-	if (!(HWREG(base + UART_O_FR) & UART_FR_TXFF))
-	{
-		HWREG(base + UART_O_DR) = ch;
-		return true;
-	}
-	return false;
-}
+#if CONFIG_KDEBUG_PORT == 0
+	#define UART_BASE UART0_BASE
+	#define UART_GPIO_BASE GPIO_PORTA_BASE
+	#define UART_PINS (BV(1) | BV(0))
+	#define UART_REG_SYSCTL SYSCTL_RCGC2_GPIOA
+#elif CONFIG_KDEBUG_PORT == 1
+	#define UART_BASE UART1_BASE
+	#define UART_GPIO_BASE GPIO_PORTD_BASE
+	#define UART_PINS (BV(3) | BV(2))
+	#define UART_REG_SYSCTL SYSCTL_RCGC2_GPIOD
+#elif CONFIG_KDEBUG_PORT == 2
+	#define UART_BASE UART2_BASE
+	#define UART_GPIO_BASE GPIO_PORTG_BASE
+	#define UART_PINS (BV(1) | BV(0))
+	#define UART_REG_SYSCTL SYSCTL_RCGC2_GPIOG
+#else
+	#error "UART port not supported in this board"
+#endif
 
-#if CONFIG_KDEBUG_PORT == KDEBUG_PORT_DBGU
-#define KDBG_WAIT_READY()     while (HWREG(UART0_BASE + UART_O_FR) & UART_FR_BUSY) {}
-#define KDBG_WAIT_TXDONE()    while (!(HWREG(UART0_BASE + UART_O_FR) & UART_FR_TXFE)) {}
+#define KDBG_WAIT_READY()     while (!lm3s_uartReady(UART_BASE)) {}
+#define KDBG_WAIT_TXDONE()    while (!lm3s_uartTxDone(UART_BASE)) {}
 
-#define KDBG_WRITE_CHAR(c)    do { HWREG(UART0_BASE + UART_O_DR) = c; } while(0)
+#define KDBG_WRITE_CHAR(c)    do { lm3s_uartPutCharNonBlocking(UART_BASE, c); } while(0)
 
 /* Debug unit is used only for debug purposes so does not generate interrupts. */
 #define KDBG_MASK_IRQ(old)    do { (void)old; } while(0)
@@ -120,16 +80,45 @@ typedef uint32_t kdbg_irqsave_t;
 #error CONFIG_KDEBUG_PORT should be KDEBUG_PORT_DBGU
 #endif
 
+INLINE void uart_hw_config(void)
+{
+	unsigned long div, baud = CONFIG_KDEBUG_BAUDRATE;
+	bool hi_speed = false;
+
+	if (baud * 16 > CPU_FREQ)
+	{
+		hi_speed = true;
+		baud /= 2;
+	}
+	div = (CPU_FREQ * 8 / baud + 1) / 2;
+
+	lm3s_uartDisable(UART_BASE);
+	if (hi_speed)
+		HWREG(UART_BASE + UART_O_CTL) |= UART_CTL_HSE;
+	else
+		HWREG(UART_BASE + UART_O_CTL) &= ~UART_CTL_HSE;
+	/* Set the baud rate */
+	HWREG(UART_BASE + UART_O_IBRD) = div / 64;
+	HWREG(UART_BASE + UART_O_FBRD) = div % 64;
+	/* Set word lenght and parity */
+	HWREG(UART_BASE + UART_O_LCRH) = UART_LCRH_WLEN_8;
+	lm3s_uartClear(UART_BASE);
+	lm3s_uartEnable(UART_BASE);
+}
+
 INLINE void kdbg_hw_init(void)
 {
+	uint32_t reg_clock = 1 << CONFIG_KDEBUG_PORT;
+
 	/* Enable the peripheral clock */
-	SYSCTL_RCGC1_R |= SYSCTL_RCGC1_UART0;
-	SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;
+	SYSCTL_RCGC1_R |= reg_clock;
+	SYSCTL_RCGC2_R |= UART_REG_SYSCTL;
 	lm3s_busyWait(512);
 
-	/* Set GPIO A0 and A1 as UART pins */
-	lm3s_gpioPinConfig(GPIO_PORTA_BASE, BV(0) | BV(1),
+	/* Configure GPIO pins to work as UART pins */
+	lm3s_gpioPinConfig(UART_GPIO_BASE, UART_PINS,
 			GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
-	/* 115.200, 8-bit word, no parity, one stop bit */
-	uart_config(UART0_BASE, CONFIG_KDEBUG_BAUDRATE, UART_LCRH_WLEN_8);
+
+	/* Low-level UART configuration */
+	uart_hw_config();
 }