X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=bertos%2Fcpu%2Fcortex-m3%2Fio%2Fsam3.h;h=8b69cb4480fe2b878ab2875415d8cce2f239c925;hb=d369c385f36aae74d203f6c40ee81c80d9032bbc;hp=8e66d1e81cbab4c85fe690bbf7132cdcee97ee61;hpb=c49471ed35076929444a0a90899df4a6ee00a49a;p=bertos.git diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h index 8e66d1e8..8b69cb44 100644 --- a/bertos/cpu/cortex-m3/io/sam3.h +++ b/bertos/cpu/cortex-m3/io/sam3.h @@ -127,26 +127,21 @@ #define USART_HAS_PDC 1 #define SPI_HAS_PDC 1 -/* PDC registers */ -#define PERIPH_RPR_OFF 0x100 // Receive Pointer Register. -#define PERIPH_RCR_OFF 0x104 // Receive Counter Register. -#define PERIPH_TPR_OFF 0x108 // Transmit Pointer Register. -#define PERIPH_TCR_OFF 0x10C // Transmit Counter Register. -#define PERIPH_RNPR_OFF 0x110 // Receive Next Pointer Register. -#define PERIPH_RNCR_OFF 0x114 // Receive Next Counter Register. -#define PERIPH_TNPR_OFF 0x118 // Transmit Next Pointer Register. -#define PERIPH_TNCR_OFF 0x11C // Transmit Next Counter Register. -#define PERIPH_PTCR_OFF 0x120 // PDC Transfer Control Register. -#define PERIPH_PTSR_OFF 0x124 // PDC Transfer Status Register. - -#define PDC_RXTEN 0 -#define PDC_RXTDIS 1 -#define PDC_TXTEN 8 -#define PDC_TXTDIS 9 - +#if CPU_CM3_SAM3X || CPU_CM3_SAM3U + #define USART_PORTS 1 + #define UART_PORTS 4 +#elif CPU_CM3_SAM3N || CPU_CM3_SAM3S + #define USART_PORTS 2 + #define UART_PORTS 2 +#else + #error undefined U(S)ART_PORTS for this cpu +#endif #include "sam3_sysctl.h" +#include "sam3_pdc.h" #include "sam3_pmc.h" +#include "sam3_smc.h" +#include "sam3_sdramc.h" #include "sam3_ints.h" #include "sam3_pio.h" #include "sam3_nvic.h" @@ -155,27 +150,88 @@ #include "sam3_spi.h" #include "sam3_flash.h" #include "sam3_wdt.h" +#include "sam3_emac.h" +#include "sam3_rstc.h" +#include "sam3_adc.h" +#include "sam3_dacc.h" +#include "sam3_tc.h" +#include "sam3_twi.h" +#include "sam3_ssc.h" /** - * UART I/O pins + * U(S)ART I/O pins */ /*\{*/ #if CPU_CM3_SAM3U - #define RXD0 11 - #define TXD0 12 + #define UART0_PORT PIOA_BASE + #define USART0_PORT PIOA_BASE + #define USART1_PORT PIOA_BASE + #define USART2_PORT PIOA_BASE + #define USART3_PORT PIOC_BASE + + #define UART0_PERIPH PIO_PERIPH_A + #define USART0_PERIPH PIO_PERIPH_A + #define USART1_PERIPH PIO_PERIPH_A + #define USART2_PERIPH PIO_PERIPH_A + #define USART3_PERIPH PIO_PERIPH_B + + #define URXD0 11 + #define UTXD0 12 + #define RXD0 19 + #define TXD0 18 + #define RXD1 21 + #define TXD1 20 + #define RXD2 23 + #define TXD2 22 + #define RXD3 13 + #define TXD3 12 #elif CPU_CM3_SAM3X - #define RXD0 8 - #define TXD0 9 -#else - #define RXD0 9 - #define TXD0 10 - #define RXD1 2 - #define TXD1 3 + #define UART0_PORT PIOA_BASE + #define USART0_PORT PIOA_BASE + #define USART1_PORT PIOA_BASE + #define USART2_PORT PIOB_BASE + #define USART3_PORT PIOD_BASE + + #define UART0_PERIPH PIO_PERIPH_A + #define USART0_PERIPH PIO_PERIPH_A + #define USART1_PERIPH PIO_PERIPH_A + #define USART2_PERIPH PIO_PERIPH_A + #define USART3_PERIPH PIO_PERIPH_B + + #define URXD0 8 + #define UTXD0 9 + #define RXD0 10 + #define TXD0 11 + #define RXD1 12 + #define TXD1 13 + #define RXD2 21 + #define TXD2 20 + #define RXD3 5 + #define TXD3 4 +#elif CPU_CM3_SAM3N || CPU_CM3_SAM3S + #define UART0_PORT PIOA_BASE + #define UART1_PORT PIOB_BASE + #define USART0_PORT PIOA_BASE + #define USART1_PORT PIOA_BASE + + #define UART0_PERIPH PIO_PERIPH_A + #define UART1_PERIPH PIO_PERIPH_A + #define USART0_PERIPH PIO_PERIPH_A + #define USART1_PERIPH PIO_PERIPH_A + + #define URXD0 9 + #define UTXD0 10 + #define URXD1 2 + #define UTXD1 3 + #define RXD0 5 + #define TXD0 6 + #define RXD1 21 + #define TXD1 22 #endif /*\}*/ /** - * PIO I/O pins + * SPI I/O pins */ /*\{*/ #if CPU_CM3_SAM3U @@ -191,5 +247,94 @@ #define SPI0_MOSI 13 #define SPI0_MISO 12 #endif +/*\}*/ + +/** + * TWI I/O pins + */ +/*\{*/ +#if CPU_CM3_SAM3X + #define TWI0_PORT PIOA_BASE + #define TWI1_PORT PIOA_BASE + + #define TWI0_PERIPH PIO_PERIPH_A + #define TWI1_PERIPH PIO_PERIPH_A + + #define TWI0_TWD 17 + #define TWI0_TWCK 18 + #define TWI1_TWD 12 + #define TWI1_TWCK 13 +#elif CPU_CM3_SAM3N || CPU_CM3_SAM3S + #define TWI0_PORT PIOA_BASE + #define TWI1_PORT PIOB_BASE + + #define TWI0_PERIPH PIO_PERIPH_A + #define TWI1_PERIPH PIO_PERIPH_A + + #define TWI0_TWD 3 + #define TWI0_TWCK 4 + #define TWI1_TWD 4 + #define TWI1_TWCK 5 +#elif CPU_CM3_SAM3U + #define TWI0_PORT PIOA_BASE + #define TWI1_PORT PIOA_BASE + + #define TWI0_PERIPH PIO_PERIPH_A + #define TWI1_PERIPH PIO_PERIPH_A + + #define TWI0_TWD 9 + #define TWI0_TWCK 10 + #define TWI1_TWD 24 + #define TWI1_TWCK 25 +#endif + +#if CPU_CM3_SAM3X + #define SSC_PORT PIOA_BASE + #define SSC_PIO_PDR PIOA_PDR + #define SSC_RECV_PERIPH PIO_PERIPH_A + #define SSC_TRAN_PERIPH PIO_PERIPH_B + #define SSC_RD 18 + #define SSC_RF 17 + #define SSC_RK 19 + #define SSC_TD 16 + #define SSC_TF 15 + #define SSC_TK 14 +#elif CPU_CM3_SAM3N + #define SSC_PORT /* None! */ + #define SSC_PIO_PDR /* None! */ + #define SSC_RECV_PERIPH /* None! */ + #define SSC_TRAN_PERIPH /* None! */ + #define SSC_RD /* None! */ + #define SSC_RF /* None! */ + #define SSC_RK /* None! */ + #define SSC_TD /* None! */ + #define SSC_TF /* None! */ + #define SSC_TK /* None! */ +#elif CPU_CM3_SAM3S + #define SSC_PORT PIOA_BASE + #define SSC_PIO_PDR PIOA_PDR + #define SSC_RECV_PERIPH PIO_PERIPH_A + #define SSC_TRAN_PERIPH PIO_PERIPH_A + #define SSC_RD 18 + #define SSC_RF 20 + #define SSC_RK 19 + #define SSC_TD 17 + #define SSC_TF 15 + #define SSC_TK 16 +#elif CPU_CM3_SAM3U + #define SSC_PORT PIOA_BASE + #define SSC_PIO_PDR PIOA_PDR + #define SSC_RECV_PERIPH PIO_PERIPH_A + #define SSC_TRAN_PERIPH PIO_PERIPH_A + #define SSC_RD 27 + #define SSC_RF 31 + #define SSC_RK 29 + #define SSC_TD 26 + #define SSC_TF 30 + #define SSC_TK 28 +#else + #error no ssc pins are defined for this cpu +#endif + /*\}*/ #endif /* SAM3_H */