X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=bertos%2Fcpu%2Firq.h;h=011524b8f098bd874ab38d967aea34f6bde31426;hb=e62ca0b357f09804d7d894949df44224c9d74bb7;hp=15609d76363d78ff7642dc78979f9200779589ed;hpb=345f93de1963f49bdb194d2b06c8c5d7ba0a3e5f;p=bertos.git

diff --git a/bertos/cpu/irq.h b/bertos/cpu/irq.h
index 15609d76..011524b8 100644
--- a/bertos/cpu/irq.h
+++ b/bertos/cpu/irq.h
@@ -34,7 +34,7 @@
  * \brief CPU-specific IRQ definitions.
  *
  * \author Giovanni Bajo <rasky@develer.com>
- * \author Bernardo Innocenti <bernie@develer.com>
+ * \author Bernie Innocenti <bernie@codewiz.org>
  * \author Stefano Fedrigo <aleph@develer.com>
  * \author Francesco Sacchi <batt@develer.com>
  */
@@ -60,8 +60,8 @@
 		#define IRQ_RESTORE(x)          FIXME
 	#endif /* OS_EMBEDDED */
 
-#elif CPU_ARM
 
+#elif CPU_ARM
 
 	#ifdef __IAR_SYSTEMS_ICC__
 
@@ -69,8 +69,8 @@
 
 		#if __CPU_MODE__ == 1 /* Thumb */
 			/* Use stubs */
-			extern cpuflags_t get_CPSR(void);
-			extern void set_CPSR(cpuflags_t flags);
+			extern cpu_flags_t get_CPSR(void);
+			extern void set_CPSR(cpu_flags_t flags);
 		#else
 			#define get_CPSR __get_CPSR
 			#define set_CPSR __set_CPSR
@@ -93,8 +93,6 @@
 		#define IRQ_ENABLED() \
 			((bool)(get_CPSR() & 0xb0))
 
-		#define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
-
 	#else /* !__IAR_SYSTEMS_ICC__ */
 
 		#define IRQ_DISABLE \
@@ -140,7 +138,7 @@
 
 		#define CPU_READ_FLAGS() \
 		({ \
-			cpuflags_t sreg; \
+			cpu_flags_t sreg; \
 			asm volatile ( \
 				"mrs %0, cpsr\n\t" \
 				: "=r" (sreg) \
@@ -154,15 +152,19 @@
 	#endif /* !__IAR_SYSTEMS_ICC_ */
 
 #elif CPU_PPC
-	#define IRQ_DISABLE         FIXME
-	#define IRQ_ENABLE          FIXME
-	#define IRQ_SAVE_DISABLE(x) FIXME
-	#define IRQ_RESTORE(x)      FIXME
-	#define IRQ_ENABLED()       FIXME
+
+	/* Get IRQ_* definitions from the hosting environment. */
+	#include <cfg/os.h>
+	#if OS_EMBEDDED
+		#define IRQ_DISABLE         FIXME
+		#define IRQ_ENABLE          FIXME
+		#define IRQ_SAVE_DISABLE(x) FIXME
+		#define IRQ_RESTORE(x)      FIXME
+		#define IRQ_ENABLED()       FIXME
+	#endif /* OS_EMBEDDED */
 
 #elif CPU_DSP56K
 
-	#define BREAKPOINT              asm(debug)
 	#define IRQ_DISABLE             do { asm(bfset #0x0200,SR); asm(nop); } while (0)
 	#define IRQ_ENABLE              do { asm(bfclr #0x0200,SR); asm(nop); } while (0)
 
@@ -228,6 +230,27 @@
 	#define IRQ_EXIT() /* NOP */
 #endif
 
+#ifdef IRQ_RUNNING
+	/// Ensure callee is running within an interrupt
+	#define ASSERT_IRQ_CONTEXT()  ASSERT(IRQ_RUNNING())
+
+	/// Ensure callee is not running within an interrupt
+	#define ASSERT_USER_CONTEXT() ASSERT(!IRQ_RUNNING())
+#else
+	#define ASSERT_USER_CONTEXT()  do {} while(0)
+	#define ASSERT_IRQ_CONTEXT()   do {} while(0)
+#endif
+
+#ifdef IRQ_ENABLED
+	/// Ensure interrupts are enabled
+	#define IRQ_ASSERT_ENABLED()  ASSERT(IRQ_ENABLED())
+
+	/// Ensure interrupts are not enabled
+	#define IRQ_ASSERT_DISABLED() ASSERT(!IRQ_ENABLED())
+#else
+	#define IRQ_ASSERT_ENABLED() do {} while(0)
+	#define IRQ_ASSERT_DISABLED() do {} while(0)
+#endif
 
 /**
  * Execute \a CODE atomically with respect to interrupts.
@@ -236,16 +259,10 @@
  */
 #define ATOMIC(CODE) \
 	do { \
-		cpuflags_t __flags; \
+		cpu_flags_t __flags; \
 		IRQ_SAVE_DISABLE(__flags); \
 		CODE; \
 		IRQ_RESTORE(__flags); \
 	} while (0)
 
-
-#ifndef BREAKPOINT
-#define BREAKPOINT /* nop */
-#endif
-
-
 #endif /* CPU_IRQ_H */