X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=cpu%2Farm%2Fio%2Fat91_us.h;h=20541a762c96551ab4a42f0e33c1e7c781c5536a;hb=791e167e053bdd9250d34a9a5ccae6ccde4d6679;hp=5819e41b891d33e037ab5deb0c1d72e857c64ccf;hpb=dcaa0c9ebc15109ea273bba4aa8eab5bade3f644;p=bertos.git

diff --git a/cpu/arm/io/at91_us.h b/cpu/arm/io/at91_us.h
index 5819e41b..20541a76 100644
--- a/cpu/arm/io/at91_us.h
+++ b/cpu/arm/io/at91_us.h
@@ -30,7 +30,7 @@
  *
  * -->
  *
- * \version $Id: at91_aic.h 18260 2007-10-11 14:08:10Z batt $
+ * \version $Id: at91_us.h 20544 2008-02-14 12:15:57Z batt $
  *
  * \author Daniele Basile <asterix@develer.com>
  *
@@ -79,7 +79,7 @@
 #define US_CR_OFF               0x00000000      ///< USART control register offset.
 #define US0_CR  (*((reg32_t *)(USART0_BASE + US_CR_OFF)))       ///< Channel 0 control register address.
 #define US1_CR  (*((reg32_t *)(USART1_BASE + US_CR_OFF)))       ///< Channel 1 control register address.
-#define US_RSTRX                         2      ///< Reset receiver. */
+#define US_RSTRX                         2      ///< Reset receiver.
 #define US_RSTTX                         3      ///< Reset transmitter.
 #define US_RXEN                          4      ///< Receiver enable.
 #define US_RXDIS                         5      ///< Receiver disable.
@@ -91,7 +91,7 @@
 #define US_STTTO                         11     ///< Start timeout.
 #define US_SENDA                         12     ///< Send next byte with address bit set.
 #define US_RSTIT                         13     ///< Reset interations.
-#define US_RTSNAK                        14     ///< Reset non acknowledge.
+#define US_RSTNAK                        14     ///< Reset non acknowledge.
 #define US_RETTO                         15     ///< Rearm time out.
 #define US_DTREN                         16     ///< Data terminal ready enable.
 #define US_DTRDIS                        17     ///< Data terminal ready disable.
@@ -284,16 +284,16 @@
 #if USART_HAS_PDC
 
 	/**
-	* Receive Pointer Register
-	*/
+	 * Receive Pointer Register
+	 */
 	/*\{*/
 	#define US0_RPR (*((reg32_t *)(USART0_BASE + PERIPH_RPR_OFF)))      ///< Channel 0 receive pointer register address.
 	#define US1_RPR (*((reg32_t *)(USART1_BASE + PERIPH_RPR_OFF)))      ///< Channel 1 receive pointer register address.
 	/*\}*/
 
 	/**
-	* Receive Counter Register
-	*/
+	 * Receive Counter Register
+	 */
 	/*\{*/
 	#define US0_RCR (*((reg32_t *)(USART0_BASE + PERIPH_RCR_OFF)))      ///< Channel 0 receive counter register address.
 	#define US1_RCR (*((reg32_t *)(USART1_BASE + PERIPH_RCR_OFF)))      ///< Channel 1 receive counter register address.
@@ -341,5 +341,4 @@
 
 #endif  /* USART_HAS_PDC */
 
-
 #endif /* AT91_US_H */