X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=cpu.h;h=4d3a5efb9d0f84358b6fd319a101d15e70b2469d;hb=07ee6a130e74de0a7fd3267eb16cdb5239d0818d;hp=4b762449c9adc67a295d5fcb8aef9b03f0aff382;hpb=6cbc8596a105e183d9f805a6deb4fae224e9baac;p=bertos.git diff --git a/cpu.h b/cpu.h index 4b762449..4d3a5efb 100755 --- a/cpu.h +++ b/cpu.h @@ -17,6 +17,27 @@ /*#* *#* $Log$ + *#* Revision 1.23 2004/11/16 22:41:58 bernie + *#* Support 64bit CPUs. + *#* + *#* Revision 1.22 2004/11/16 21:57:59 bernie + *#* CPU_IDLE: Rename from SCHEDULER_IDLE. + *#* + *#* Revision 1.21 2004/11/16 21:34:25 bernie + *#* Commonize obsolete names for IRQ macros; Doxygen fixes. + *#* + *#* Revision 1.20 2004/11/16 20:33:32 bernie + *#* CPU_HARVARD: New macro. + *#* + *#* Revision 1.19 2004/10/03 20:43:54 bernie + *#* Fix Doxygen markup. + *#* + *#* Revision 1.18 2004/10/03 18:36:31 bernie + *#* IRQ_GETSTATE(): New macro; Rename IRQ macros for consistency. + *#* + *#* Revision 1.17 2004/09/06 21:48:27 bernie + *#* ATOMIC(): New macro. + *#* *#* Revision 1.16 2004/08/29 21:58:33 bernie *#* Rename BITS_PER_XYZ macros; Add sanity checks. *#* @@ -45,19 +66,23 @@ #include "compiler.h" /* for uintXX_t, PP_CAT3(), PP_STRINGIZE() */ -// Macros for determining CPU endianness +/*! + * \name Macros for determining CPU endianness. + * \{ + */ #define CPU_BIG_ENDIAN 0x1234 #define CPU_LITTLE_ENDIAN 0x3412 +/*\}*/ -// Macros to include cpu-specific version of the headers +/*! Macro to include cpu-specific versions of the headers. */ #define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h) #if CPU_I196 - #define DISABLE_INTS disable_interrupt() - #define ENABLE_INTS enable_interrupt() #define NOP nop_instruction() + #define IRQ_DISABLE disable_interrupt() + #define IRQ_ENABLE enable_interrupt() typedef uint16_t cpuflags_t; // FIXME typedef unsigned int cpustack_t; @@ -67,12 +92,13 @@ #define CPU_STACK_GROWS_UPWARD 0 #define CPU_SP_ON_EMPTY_SLOT 0 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN + #define CPU_HARVARD 0 #elif CPU_X86 #define NOP asm volatile ("nop") - #define DISABLE_INTS /* nothing */ - #define ENABLE_INTS /* nothing */ + #define IRQ_DISABLE /* nothing */ + #define IRQ_ENABLE /* nothing */ typedef uint32_t cpuflags_t; // FIXME typedef uint32_t cpustack_t; @@ -82,18 +108,20 @@ #define CPU_STACK_GROWS_UPWARD 0 #define CPU_SP_ON_EMPTY_SLOT 0 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN + #define CPU_HARVARD 0 #elif CPU_DSP56K #define NOP asm(nop) - #define DISABLE_INTS do { asm(bfset #0x0200,SR); asm(nop); } while (0) - #define ENABLE_INTS do { asm(bfclr #0x0200,SR); asm(nop); } while (0) + #define IRQ_DISABLE do { asm(bfset #0x0200,SR); asm(nop); } while (0) + #define IRQ_ENABLE do { asm(bfclr #0x0200,SR); asm(nop); } while (0) - #define DISABLE_IRQSAVE(x) \ + #define IRQ_SAVE_DISABLE(x) \ do { (void)x; asm(move SR,x); asm(bfset #0x0200,SR); } while (0) - #define ENABLE_IRQRESTORE(x) \ + #define IRQ_RESTORE(x) \ do { (void)x; asm(move x,SR); } while (0) + typedef uint16_t cpuflags_t; typedef unsigned int cpustack_t; @@ -113,11 +141,11 @@ #elif CPU_AVR - #define NOP asm volatile ("nop" ::) - #define DISABLE_INTS asm volatile ("cli" ::) - #define ENABLE_INTS asm volatile ("sei" ::) + #define NOP asm volatile ("nop" ::) + #define IRQ_DISABLE asm volatile ("cli" ::) + #define IRQ_ENABLE asm volatile ("sei" ::) - #define DISABLE_IRQSAVE(x) \ + #define IRQ_SAVE_DISABLE(x) \ do { \ __asm__ __volatile__( \ "in %0,__SREG__\n\t" \ @@ -126,13 +154,23 @@ ); \ } while (0) - #define ENABLE_IRQRESTORE(x) \ + #define IRQ_RESTORE(x) \ do { \ __asm__ __volatile__( \ "out __SREG__,%0" : /* no outputs */ : "r" (x) : "cc" \ ); \ } while (0) + #define IRQ_GETSTATE() \ + ({ \ + uint8_t sreg; \ + __asm__ __volatile__( \ + "in %0,__SREG__\n\t" \ + : "=r" (sreg) /* no inputs & no clobbers */ \ + ); \ + (bool)(sreg & 0x80); \ + }) + typedef uint8_t cpuflags_t; typedef uint8_t cpustack_t; @@ -154,6 +192,25 @@ #endif +/* OBSOLETE NAMES */ +#define DISABLE_INTS IRQ_DISABLE +#define ENABLE_INTS IRQ_ENABLE +#define DISABLE_IRQSAVE(x) IRQ_SAVE_DISABLE(x) +#define ENABLE_IRQRESTORE(x) IRQ_RESTORE(x) + +/*! + * Execute \a CODE atomically with respect to interrupts. + * + * \see ENABLE_IRQSAVE DISABLE_IRQRESTORE + */ +#define ATOMIC(CODE) \ + do { \ + cpuflags_t __flags; \ + DISABLE_IRQSAVE(__flags); \ + CODE; \ + ENABLE_IRQRESTORE(__flags); \ + } while (0) + //! Default for macro not defined in the right arch section #ifndef CPU_REG_INIT_VALUE @@ -205,7 +262,8 @@ #if CPU_DSP56K - /* DSP56k pushes both PC and SR to the stack in the JSR instruction, but + /* + * DSP56k pushes both PC and SR to the stack in the JSR instruction, but * RTS discards SR while returning (it does not restore it). So we push * 0 to fake the same context. */ @@ -216,7 +274,8 @@ } while (0); #elif CPU_AVR - /* In AVR, the addresses are pushed into the stack as little-endian, while + /* + * In AVR, the addresses are pushed into the stack as little-endian, while * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is * no natural endianess). */ @@ -251,7 +310,7 @@ * CPU_BITS_PER_SHORT >= 8 * CPU_BITS_PER_INT >= 16 * CPU_BITS_PER_LONG >= 32 - * \end code + * \endcode * \{ */ #ifndef SIZEOF_CHAR @@ -271,7 +330,11 @@ #endif /* !SIZEOF_INT */ #ifndef SIZEOF_LONG -#define SIZEOF_LONG 4 +#if CPU_REG_BITS > 32 + #define SIZEOF_LONG 8 +#else + #define SIZEOF_LONG 4 +#endif #endif #ifndef SIZEOF_PTR @@ -315,16 +378,19 @@ STATIC_ASSERT(sizeof(int) == SIZEOF_INT); * profile system load with an external strobe, or to save CPU cycles * in hosted environments such as emulators. */ -#ifndef SCHEDULER_IDLE +#ifndef CPU_IDLE #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL) /* This emulator hook should yield the CPU to the host. */ EXTERN_C_BEGIN void SchedulerIdle(void); EXTERN_C_END - #define SCHEDULER_IDLE SchedulerIdle() + #define CPU_IDLE SchedulerIdle() #else /* !ARCH_EMUL */ - #define SCHEDULER_IDLE do { /* nothing */ } while (0) + #define CPU_IDLE do { /* nothing */ } while (0) #endif /* !ARCH_EMUL */ -#endif /* !SCHEDULER_IDLE */ +#endif /* !CPU_IDLE */ + +/* OBSOLETE */ +#define SCHEDULER_IDLE CPU_IDLE #endif /* DEVLIB_CPU_H */