X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=drv%2Fser_dsp56k.c;h=6c75f8a348457a78f58b7cf4e99bbba7e53540d7;hb=c273ae81bac91c7eaaecb71482992803539dd0eb;hp=d2f1362041180fbed8d63d242a369dad190ca174;hpb=0375780817109b6ab5cd4f36ccf80650b2fe77d5;p=bertos.git diff --git a/drv/ser_dsp56k.c b/drv/ser_dsp56k.c index d2f13620..6c75f8a3 100755 --- a/drv/ser_dsp56k.c +++ b/drv/ser_dsp56k.c @@ -1,20 +1,33 @@ -/** +/*! * \file - * Copyright (C) 2003 Develer S.r.l. (http://www.develer.com/) - * All Rights Reserved. + * * * \version $Id$ * * \author Stefano Fedrigo + * \author Giovanni Bajo * * \brief DSP5680x CPU specific serial I/O driver */ -#include -#include -#include +/* + * $Log$ + * Revision 1.3 2004/06/03 11:27:09 bernie + * Add dual-license information. + * + * Revision 1.2 2004/05/23 18:21:53 bernie + * Trim CVS logs and cleanup header info. + * + */ + #include "ser.h" #include "ser_p.h" +#include +#include +#include // GPIO E is shared with SPI (in DSP56807). Pins 0&1 are TXD0 and RXD0. To use // the serial, we need to disable the GPIO functions on them. @@ -101,16 +114,16 @@ INLINE void rx_isr(struct SCI *hw) { volatile struct REG_SCI_STRUCT* regs = hw->regs; - hw->serial->status |= regs->SR & (SERRF_PARITYERROR | - SERRF_RXSROVERRUN | - SERRF_FRAMEERROR | + hw->serial->status |= regs->SR & (SERRF_PARITYERROR | + SERRF_RXSROVERRUN | + SERRF_FRAMEERROR | SERRF_NOISEERROR); - + if (fifo_isfull(&hw->serial->rxfifo)) hw->serial->status |= SERRF_RXFIFOOVERRUN; else fifo_push(&hw->serial->rxfifo, regs->DR); - + // Writing anything to the status register clear the // error bits. regs->SR = 0; @@ -124,10 +137,10 @@ static void init(struct SerialHardware* _hw, struct Serial* ser) // Clear status register (IRQ/status flags) (void)regs->SR; regs->SR = 0; - + // Clear data register (void)regs->DR; - + // Set priorities for both IRQs irq_setpriority(hw->irq_tx, IRQ_PRIORITY_SCI_TX); irq_setpriority(hw->irq_rx, IRQ_PRIORITY_SCI_RX); @@ -135,7 +148,7 @@ static void init(struct SerialHardware* _hw, struct Serial* ser) // Activate the RX error interrupts, and RX/TX transmissions regs->CR = REG_SCI_CR_TE | REG_SCI_CR_RE; enable_rx_irq_bare(regs); - + // Disable GPIO pins for TX and RX lines REG_GPIO_SERIAL->PER |= REG_GPIO_SERIAL_MASK; @@ -176,19 +189,19 @@ static const struct SerialHardwareVT SCI_VT = static struct SCI SCIDescs[2] = { - { - .hw = { .table = &SCI_VT }, - .regs = ®_SCI[0], - .irq_rx = IRQ_SCI0_RECEIVER_FULL, - .irq_tx = IRQ_SCI0_TRANSMITTER_READY, - }, - - { - .hw = { .table = &SCI_VT }, + { + .hw = { .table = &SCI_VT }, + .regs = ®_SCI[0], + .irq_rx = IRQ_SCI0_RECEIVER_FULL, + .irq_tx = IRQ_SCI0_TRANSMITTER_READY, + }, + + { + .hw = { .table = &SCI_VT }, .regs = ®_SCI[1], - .irq_rx = IRQ_SCI1_RECEIVER_FULL, - .irq_tx = IRQ_SCI1_TRANSMITTER_READY, - }, + .irq_rx = IRQ_SCI1_RECEIVER_FULL, + .irq_tx = IRQ_SCI1_TRANSMITTER_READY, + }, };