X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;ds=sidebyside;f=examples%2Ftriface%2Fhw%2Fhw_sipo.h;fp=examples%2Ftriface%2Fhw%2Fhw_sipo.h;h=0000000000000000000000000000000000000000;hb=ccd15e30330f168e9c48aab01b8efb81e4b39998;hp=9922c0520d3896cfa333959a2d33afc815514141;hpb=391b4f8d9c82c413f2cd11fb3ba3aeb311f62184;p=bertos.git diff --git a/examples/triface/hw/hw_sipo.h b/examples/triface/hw/hw_sipo.h deleted file mode 100644 index 9922c052..00000000 --- a/examples/triface/hw/hw_sipo.h +++ /dev/null @@ -1,149 +0,0 @@ -/** - * \file - * - * - * \brief Macro for HW_SIPO_H - * - * - * \author Andrea Grandi - * \author Daniele Basile - */ - -#ifndef HW_SIPO_H -#define HW_SIPO_H - -#include - -#include - -/** - * Mapping sipo connection on board. - * See schematics for more info. - */ -typedef enum SipoMap -{ - TRIFACE_DOUT = 0, - - SIPO_CNT -} SipoMap; - - - -//Set output pin for sipo -#define SCK_OUT (DDRB |= BV(PB1)) // Shift register clock input pin -#define SOUT_OUT (DDRB |= BV(PB2)) // Serial data input pin -#define SLOAD_OUT (DDRB |= BV(PB3)) // Storage register clock input pin -#define OE_OUT (DDRG |= BV(PG3)) // Output enable pin - -//Define output level -#define SCK_HIGH (PORTB |= BV(PB1)) -#define SCK_LOW (PORTB &= ~BV(PB1)) -#define SOUT_OUT_HIGH (PORTB |= BV(PB2)) -#define SOUT_OUT_LOW (PORTB &= ~BV(PB2)) -#define SLOAD_OUT_HIGH (PORTB |= BV(PB3)) -#define SLOAD_OUT_LOW (PORTB &= ~BV(PB3)) -#define OE_LOW (PORTG &= BV(PG3)) - -/** - * Define the macros needed to set the serial input bit of SIPO device - * low or high. - */ -#define SIPO_SI_HIGH() SOUT_OUT_HIGH -#define SIPO_SI_LOW() SOUT_OUT_LOW - -/** - * Drive pin to load the bit, presented in serial-in pin, - * into sipo shift register. - */ -#define SIPO_SI_CLOCK(clk_pol) \ - do{ \ - (void)clk_pol; \ - SCK_HIGH; \ - SCK_LOW; \ - }while(0) - -/** - * Clock the content of shift register to output. - */ -#define SIPO_LOAD(device, load_pol) \ - do { \ - (void)device; \ - (void)load_pol; \ - SLOAD_OUT_HIGH; \ - SLOAD_OUT_LOW; \ - }while(0) - -/** - * Enable the shift register output. - */ -#define SIPO_ENABLE() OE_LOW; - -/** - * Set logic level for load signal - */ -#define SIPO_SET_LD_LEVEL(device, load_pol) \ - do { \ - (void)device; \ - if(load_pol) \ - SLOAD_OUT_HIGH; \ - else \ - SLOAD_OUT_LOW; \ - } while (0) - - -/** - * Sel logic level for clock signal - */ -#define SIPO_SET_CLK_LEVEL(clock_pol) \ - do { \ - if(clock_pol) \ - SCK_HIGH; \ - else \ - SCK_LOW; \ - } while (0) - -#define SIPO_SET_SI_LEVEL() SIPO_SI_LOW() - -/** - * Do everything needed in order to init the SIPO pins. - */ -#define SIPO_INIT_PIN() \ - do { \ - OE_OUT; \ - SOUT_OUT; \ - SCK_OUT; \ - SLOAD_OUT; \ - SIPO_ENABLE(); \ - } while(0) - - -#endif /* HW_SIPO_H */