X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=app%2Ftriface%2Fboot%2Fcfg%2Fcfg_ser.h;fp=app%2Ftriface%2Fboot%2Fcfg%2Fcfg_ser.h;h=0000000000000000000000000000000000000000;hb=24c21c92d29b76a3f0de0a107f4bafef7bb0f812;hp=eb11a4cb55edb3ee5f37d0c5c59b74c67d43e959;hpb=6b7a2e7b20bc7fe05a61c17d6d96eb70c67a09c9;p=bertos.git diff --git a/app/triface/boot/cfg/cfg_ser.h b/app/triface/boot/cfg/cfg_ser.h deleted file mode 100644 index eb11a4cb..00000000 --- a/app/triface/boot/cfg/cfg_ser.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - * \file - * - * - * \brief Configuration file for serial module. - * - * \version $Id$ - * - * \author Daniele Basile - */ - -#ifndef CFG_SER_H -#define CFG_SER_H - - -/// Kdebug console on debug unit -#define CONFIG_TRIFACE_PORT 0 - -/// Baud-rate for the kdebug console -#define CONFIG_TRIFACE_BAUDRATE 115200 - -/// [bytes] Size of the outbound FIFO buffer for port 0. -#define CONFIG_UART0_TXBUFSIZE 32 - -/// [bytes] Size of the inbound FIFO buffer for port 0. -#define CONFIG_UART0_RXBUFSIZE 64 - -/// [bytes] Size of the outbound FIFO buffer for port 1. -#define CONFIG_UART1_TXBUFSIZE 32 - -/// [bytes] Size of the inbound FIFO buffer for port 1. -#define CONFIG_UART1_RXBUFSIZE 64 - - -/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only) -#define CONFIG_SPI_TXBUFSIZE 32 - -/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only) -#define CONFIG_SPI_RXBUFSIZE 32 - -/// [bytes] Size of the outbound FIFO buffer for SPI port 0. -#define CONFIG_SPI0_TXBUFSIZE 32 - -/// [bytes] Size of the inbound FIFO buffer for SPI port 0. -#define CONFIG_SPI0_RXBUFSIZE 32 - -/// [bytes] Size of the outbound FIFO buffer for SPI port 1. -#define CONFIG_SPI1_TXBUFSIZE 32 - -/// [bytes] Size of the inbound FIFO buffer for SPI port 1. -#define CONFIG_SPI1_RXBUFSIZE 32 - -/// SPI data order (AVR only). -#define CONFIG_SPI_DATA_ORDER SER_MSB_FIRST - -/// SPI clock division factor (AVR only). -#define CONFIG_SPI_CLOCK_DIV 16 - -/// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only). -#define CONFIG_SPI_CLOCK_POL 0 - -/// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only). -#define CONFIG_SPI_CLOCK_PHASE 0 - -/// Default transmit timeout (ms). Set to -1 to disable timeout support. -#define CONFIG_SER_TXTIMEOUT 100 - -/// Default receive timeout (ms). Set to -1 to disable timeout support. -#define CONFIG_SER_RXTIMEOUT 100 - -/// Use RTS/CTS handshake -#define CONFIG_SER_HWHANDSHAKE 0 - -/// Default baud rate (set to 0 to disable). -#define CONFIG_SER_DEFBAUDRATE 0 - -/// Enable second serial port in emulator. -#define CONFIG_EMUL_UART1 0 - -/** - * Transmit always something on serial port 0 TX - * to avoid interference when sending burst of data, - * using AVR multiprocessor serial mode - */ -#define CONFIG_SER_TXFILL 0 - -/// For serial debug. -#define CONFIG_SER_STROBE 0 - -#endif /* CFG_SER_H */