X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcfg%2Fcfg_adc.h;h=62ee6ed73f34bc223e71e3c0d47003c48fc3b704;hb=56f2c002c50338f23f1b969ba51a43b0eb24f3da;hp=26254a41573899b5b6834a8829e81b8566172514;hpb=bdcc52e5f18159cadc413c53dd14ef468a6de376;p=bertos.git

diff --git a/bertos/cfg/cfg_adc.h b/bertos/cfg/cfg_adc.h
index 26254a41..62ee6ed7 100644
--- a/bertos/cfg/cfg_adc.h
+++ b/bertos/cfg/cfg_adc.h
@@ -27,12 +27,10 @@
  * the GNU General Public License.
  *
  * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
- * All Rights Reserved.
- * -->
  *
- * \brief Configuration file for ADC module.
+ * -->
  *
- * \version $Id$
+ * \brief Configuration file for the ADC module.
  *
  * \author Daniele Basile <asterix@develer.com>
  */
@@ -41,41 +39,111 @@
 #define CFG_ADC_H
 
 /**
- * Logging level definition.
+ * Module logging level.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "log_level"
+ */
+#define ADC_LOG_LEVEL      LOG_LVL_INFO
+
+/**
+ * Module logging format.
  *
- * Use 0 to log only the error messages
- * Use 1 to log the error and warning messages
- * Use 2 to log all messages
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "log_format"
  */
-#define ADC_LOG_LEVEL      2
+#define ADC_LOG_FORMAT     LOG_FMT_VERBOSE
 
 /**
- * Set logging verbosity.
+ * Clock Frequency for ADC conversion.
+ * This frequency will be rounded down to an integer
+ * submultiple of CPU_FREQ.
  *
- * If verbosity is zero print short log messages.
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "at91"
+ * $WIZ$ max = 5000000
  */
-#define ADC_LOG_VERBOSITY    1
+#define CONFIG_ADC_CLOCK        4800000UL
 
+/**
+ * Minimum time for starting up a conversion [us].
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 20
+ * $WIZ$ supports = "at91"
+ */
+#define CONFIG_ADC_STARTUP_TIME 20
 
 /**
- * ADC timing setting parameter
+ * Minimum time for sample and hold [ns].
  *
- * - CONFIG_ADC_CLOCK is frequency clock for ADC conversion.
- * - CONFIG_ADC_STARTUP_TIME  minimum time for startup a conversion in micro second.
- * - CONFIG_ADC_SHTIME minimum time for sample and hold in nano second.
- * \{
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 600
+ * $WIZ$ supports = "at91"
  */
-#define CONFIG_ADC_CLOCK          4800000UL
-#define CONFIG_ADC_STARTUP_TIME        20
-#define CONFIG_ADC_SHTIME             834
-/* \ * } */
+#define CONFIG_ADC_SHTIME       834
 
-/// ADC setting for AVR target
-#define CONFIG_ADC_AVR_REF      1
+/**
+ * ADC Voltage Reference.
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "avr_adc_refs"
+ * $WIZ$ supports = "avr"
+ */
+#define CONFIG_ADC_AVR_REF      ADC_AVR_AVCC
+
+/**
+ * ADC clock divisor from main crystal.
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ max = 128
+ * $WIZ$ supports = "avr"
+ */
 #define CONFIG_ADC_AVR_DIVISOR  2
 
-/// Enable ADS strobe.
+/**
+ * Enable ADC strobe for debugging ADC ISR.
+ *
+ * $WIZ$ type = "boolean"
+ */
 #define CONFIG_ADC_STROBE  0
 
-#endif /* CFG_ADC_H */
 
+/**
+ * Start up timer[s] = startup value / ADCClock [Hz]
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "sam3_adc_sut"
+ * $WIZ$ supports = "sam3"
+ */
+#define CONFIG_ADC_SUT         ADC_SUT512
+
+/**
+ * Analog Settling Time[s] = settling value / ADCClock[Hz]
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "sam3_adc_stt"
+ * $WIZ$ supports = "sam3"
+ */
+#define CONFIG_ADC_STTLING     ADC_AST17
+
+/**
+ * Tracking Time[s] = (TRACKTIM + 1) / ADCClock[Hz]
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 0
+ * $WIZ$ supports = "sam3"
+ */
+#define CONFIG_ADC_TRACKTIM    0
+
+/**
+ * Transfer Period[s] = (TRANSFER * 2 + 3) ADCClock[Hz]
+ *
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 0
+ * $WIZ$ supports = "sam3"
+ */
+#define CONFIG_ADC_TRANSFER    1
+
+#endif /* CFG_ADC_H */