X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcfg%2Fcfg_ser.h;h=2adb55eaa382e182f1d06dc738539344e657c9c4;hb=dc965a13a04e907d341a54af95dc84329f968e0b;hp=725e5dd1b7dce98d48a41173c1503d78608eb505;hpb=9006725d9f57b31d4f4a75d4bab7ec07260f1202;p=bertos.git

diff --git a/bertos/cfg/cfg_ser.h b/bertos/cfg/cfg_ser.h
index 725e5dd1..2adb55ea 100644
--- a/bertos/cfg/cfg_ser.h
+++ b/bertos/cfg/cfg_ser.h
@@ -46,17 +46,6 @@
  * Edit these define for your project.
  */
 
-/// Serial port settings. $WIZ$ type = "int"
-#define CONFIG_SER_PORT      0
-/// Serial port baudrate. $WIZ$ type = "int"
-#define CONFIG_SER_BAUDRATE  115200UL
-
-/// Spi port settings. $WIZ$ type = "int"
-#define CONFIG_SPI_PORT      0
-/// Spi port baudrate. $WIZ$ type = "int"
-#define CONFIG_SPI_BAUDRATE  5000000UL
-
-
 /// [bytes] Size of the outbound FIFO buffer for port 0. $WIZ$ type = "int"
 #define CONFIG_UART0_TXBUFSIZE  32
 
@@ -70,10 +59,18 @@
 #define CONFIG_UART1_RXBUFSIZE  32
 
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only). $WIZ$ type = "int"
+/**
+ * [bytes] Size of the outbound FIFO buffer for SPI port.
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "avr"
+ */
 #define CONFIG_SPI_TXBUFSIZE    32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only). $WIZ$ type = "int"
+/**
+ * [bytes] Size of the inbound FIFO buffer for SPI port.
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "avr"
+ */
 #define CONFIG_SPI_RXBUFSIZE    32
 
 /// [bytes] Size of the outbound FIFO buffer for SPI port 0. $WIZ$ type = "int"
@@ -89,27 +86,35 @@
 #define CONFIG_SPI1_RXBUFSIZE	32
 
 /**
- * SPI data order (AVR only).
+ * SPI data order.
  *
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_order_bit"
+ * $WIZ$ supports = "avr"
  */
 #define CONFIG_SPI_DATA_ORDER	SER_MSB_FIRST
 
-/// SPI clock division factor (AVR only). $WIZ$ type = "int"
+/**
+ * SPI clock division factor.
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "avr"
+ */
 #define CONFIG_SPI_CLOCK_DIV	16
+
 /**
- * SPI clock polarity: normal low or normal high (AVR only).
+ * SPI clock polarity: normal low or normal high.
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_spi_pol"
+ * $WIZ$ supports = "avr"
  */
 #define CONFIG_SPI_CLOCK_POL        SPI_NORMAL_LOW
 
 /**
  * SPI clock phase you can choose sample on first edge or
- * sample on second clock edge (AVR only)
+ * sample on second clock edge.
  * $WIZ$ type = "enum"
  * $WIZ$ value_list = "ser_spi_phase"
+ * $WIZ$ supports = "avr"
  */
 #define CONFIG_SPI_CLOCK_PHASE	    SPI_SAMPLE_ON_FIRST_EDGE