X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcfg%2Fcfg_ser.h;h=725e5dd1b7dce98d48a41173c1503d78608eb505;hb=2cf01a12f0b0bb1d5666a12ad64f0212e118c8a4;hp=8fc59489ef9ec52eca83742c2ae4a8605345705f;hpb=214a3703cc92b423088cf27c4fc637e288d38e17;p=bertos.git

diff --git a/bertos/cfg/cfg_ser.h b/bertos/cfg/cfg_ser.h
index 8fc59489..725e5dd1 100644
--- a/bertos/cfg/cfg_ser.h
+++ b/bertos/cfg/cfg_ser.h
@@ -45,84 +45,93 @@
  * spi port.
  * Edit these define for your project.
  */
-/// Serial settings
+
+/// Serial port settings. $WIZ$ type = "int"
 #define CONFIG_SER_PORT      0
-#define CONFIG_SER_BAUDRATE  115200
+/// Serial port baudrate. $WIZ$ type = "int"
+#define CONFIG_SER_BAUDRATE  115200UL
 
-/// Spi settings
-#define CONFIG_SPI_PORT      SER_SPI0
+/// Spi port settings. $WIZ$ type = "int"
+#define CONFIG_SPI_PORT      0
+/// Spi port baudrate. $WIZ$ type = "int"
 #define CONFIG_SPI_BAUDRATE  5000000UL
 
 
-/// [bytes] Size of the outbound FIFO buffer for port 0.
+/// [bytes] Size of the outbound FIFO buffer for port 0. $WIZ$ type = "int"
 #define CONFIG_UART0_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 0.
+/// [bytes] Size of the inbound FIFO buffer for port 0. $WIZ$ type = "int"
 #define CONFIG_UART0_RXBUFSIZE  32
 
-/// [bytes] Size of the outbound FIFO buffer for port 1.
+/// [bytes] Size of the outbound FIFO buffer for port 1. $WIZ$ type = "int"
 #define CONFIG_UART1_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 1.
+/// [bytes] Size of the inbound FIFO buffer for port 1. $WIZ$ type = "int"
 #define CONFIG_UART1_RXBUFSIZE  32
 
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only)
+/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only). $WIZ$ type = "int"
 #define CONFIG_SPI_TXBUFSIZE    32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only)
+/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only). $WIZ$ type = "int"
 #define CONFIG_SPI_RXBUFSIZE    32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 0.
+/// [bytes] Size of the outbound FIFO buffer for SPI port 0. $WIZ$ type = "int"
 #define CONFIG_SPI0_TXBUFSIZE	32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 0.
+/// [bytes] Size of the inbound FIFO buffer for SPI port 0. $WIZ$ type = "int"
 #define CONFIG_SPI0_RXBUFSIZE	32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 1.
+/// [bytes] Size of the outbound FIFO buffer for SPI port 1. $WIZ$ type = "int"
 #define CONFIG_SPI1_TXBUFSIZE	32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 1.
+/// [bytes] Size of the inbound FIFO buffer for SPI port 1. $WIZ$ type = "int"
 #define CONFIG_SPI1_RXBUFSIZE	32
 
-/// SPI data order (AVR only).
+/**
+ * SPI data order (AVR only).
+ *
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "ser_order_bit"
+ */
 #define CONFIG_SPI_DATA_ORDER	SER_MSB_FIRST
 
-/// SPI clock division factor (AVR only).
+/// SPI clock division factor (AVR only). $WIZ$ type = "int"
 #define CONFIG_SPI_CLOCK_DIV	16
+/**
+ * SPI clock polarity: normal low or normal high (AVR only).
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "ser_spi_pol"
+ */
+#define CONFIG_SPI_CLOCK_POL        SPI_NORMAL_LOW
 
-/// SPI clock polarity: 0 = normal low, 1 = normal high (AVR only).
-#define CONFIG_SPI_CLOCK_POL	0
-
-/// SPI clock phase: 0 = sample on first edge, 1 = sample on second clock edge (AVR only).
-#define CONFIG_SPI_CLOCK_PHASE	0
+/**
+ * SPI clock phase you can choose sample on first edge or
+ * sample on second clock edge (AVR only)
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "ser_spi_phase"
+ */
+#define CONFIG_SPI_CLOCK_PHASE	    SPI_SAMPLE_ON_FIRST_EDGE
 
-/// Default transmit timeout (ms). Set to -1 to disable timeout support.
+/// Default transmit timeout (ms). Set to -1 to disable timeout support. $WIZ$ type = "int"
 #define CONFIG_SER_TXTIMEOUT    -1
 
-/// Default receive timeout (ms). Set to -1 to disable timeout support.
+/// Default receive timeout (ms). Set to -1 to disable timeout support. $WIZ$ type = "int"
 #define CONFIG_SER_RXTIMEOUT    -1
 
-/// Use RTS/CTS handshake
+/// Use RTS/CTS handshake. $WIZ$ type = "boolean"
 #define CONFIG_SER_HWHANDSHAKE   0
 
-/// Default baud rate (set to 0 to disable).
+/// Default baud rate (set to 0 to disable). $WIZ$ type = "boolean"
 #define CONFIG_SER_DEFBAUDRATE   0
 
-/// Enable ser_gets() and ser_gets_echo().
+/// Enable ser_gets() and ser_gets_echo(). $WIZ$ type = "boolean"
 #define CONFIG_SER_GETS          0
 
-/// Enable second serial port in emulator.
+/// Enable second serial port in emulator. $WIZ$ type = "boolean"
 #define CONFIG_EMUL_UART1        0
 
-/**
- * Transmit always something on serial port 0 TX
- * to avoid interference when sending burst of data,
- * using AVR multiprocessor serial mode
- */
-#define CONFIG_SER_TXFILL        0
-
-/// For serial debug.
+/// For serial debug. $WIZ$ type = "boolean"
 #define CONFIG_SER_STROBE        0
 
 #endif /* CFG_SER_H */