X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcfg%2Fcfg_ser.h;h=91a10e0b2d8ade049eeb03b95150797d6728a29f;hb=c34de402cec6fda7bf4474f32fed5e5c02cd7e7e;hp=2adb55eaa382e182f1d06dc738539344e657c9c4;hpb=dc965a13a04e907d341a54af95dc84329f968e0b;p=bertos.git

diff --git a/bertos/cfg/cfg_ser.h b/bertos/cfg/cfg_ser.h
index 2adb55ea..91a10e0b 100644
--- a/bertos/cfg/cfg_ser.h
+++ b/bertos/cfg/cfg_ser.h
@@ -32,8 +32,6 @@
  *
  * \brief Configuration file for serial module.
  *
- * \version $Id$
- *
  * \author Daniele Basile <asterix@develer.com>
  */
 
@@ -46,43 +44,115 @@
  * Edit these define for your project.
  */
 
-/// [bytes] Size of the outbound FIFO buffer for port 0. $WIZ$ type = "int"
+/**
+ * Size of the outbound FIFO buffer for port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ */
 #define CONFIG_UART0_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 0. $WIZ$ type = "int"
+/**
+ * Size of the inbound FIFO buffer for port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ */
 #define CONFIG_UART0_RXBUFSIZE  32
 
-/// [bytes] Size of the outbound FIFO buffer for port 1. $WIZ$ type = "int"
+/**
+ * Size of the outbound FIFO buffer for port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
+ */
 #define CONFIG_UART1_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 1. $WIZ$ type = "int"
+/**
+ * Size of the inbound FIFO buffer for port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2 or (at91 and not atmega8 and not atmega168 and not atmega32)"
+ */
 #define CONFIG_UART1_RXBUFSIZE  32
 
+/**
+ * Size of the outbound FIFO buffer for port 2 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2"
+ */
+#define CONFIG_UART2_TXBUFSIZE  32
+
+/**
+ * Size of the inbound FIFO buffer for port 2 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2"
+ */
+#define CONFIG_UART2_RXBUFSIZE  32
+
+/**
+ * Size of the outbound FIFO buffer for port 3 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lpc2"
+ */
+#define CONFIG_UART3_TXBUFSIZE  32
+
+/**
+ * Size of the inbound FIFO buffer for port 3 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lpc2"
+ */
+#define CONFIG_UART3_RXBUFSIZE  32
+
 
 /**
- * [bytes] Size of the outbound FIFO buffer for SPI port.
+ * Size of the outbound FIFO buffer for SPI port [bytes].
  * $WIZ$ type = "int"
+ * $WIZ$ min = 2
  * $WIZ$ supports = "avr"
  */
 #define CONFIG_SPI_TXBUFSIZE    32
 
 /**
- * [bytes] Size of the inbound FIFO buffer for SPI port.
+ * Size of the inbound FIFO buffer for SPI port [bytes].
  * $WIZ$ type = "int"
+ * $WIZ$ min = 2
  * $WIZ$ supports = "avr"
  */
 #define CONFIG_SPI_RXBUFSIZE    32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 0. $WIZ$ type = "int"
+/**
+ * Size of the outbound FIFO buffer for SPI port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "at91"
+ */
 #define CONFIG_SPI0_TXBUFSIZE	32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 0. $WIZ$ type = "int"
+/**
+ * Size of the inbound FIFO buffer for SPI port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "at91"
+ */
 #define CONFIG_SPI0_RXBUFSIZE	32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 1. $WIZ$ type = "int"
+/**
+ * Size of the outbound FIFO buffer for SPI port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "at91"
+ */
 #define CONFIG_SPI1_TXBUFSIZE	32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 1. $WIZ$ type = "int"
+/**
+ * Size of the inbound FIFO buffer for SPI port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "at91"
+ */
 #define CONFIG_SPI1_RXBUFSIZE	32
 
 /**
@@ -118,25 +188,35 @@
  */
 #define CONFIG_SPI_CLOCK_PHASE	    SPI_SAMPLE_ON_FIRST_EDGE
 
-/// Default transmit timeout (ms). Set to -1 to disable timeout support. $WIZ$ type = "int"
+/**
+ * Default transmit timeout (ms). Set to -1 to disable timeout support.
+ * $WIZ$ type = "int"
+ * $WIZ$ min = -1
+ */
 #define CONFIG_SER_TXTIMEOUT    -1
 
-/// Default receive timeout (ms). Set to -1 to disable timeout support. $WIZ$ type = "int"
+/**
+ * Default receive timeout (ms). Set to -1 to disable timeout support.
+ * $WIZ$ type = "int"
+ * $WIZ$ min = -1
+ */
 #define CONFIG_SER_RXTIMEOUT    -1
 
-/// Use RTS/CTS handshake. $WIZ$ type = "boolean"
+/**
+ * Use RTS/CTS handshake.
+ * $WIZ$ type = "boolean"
+ * $WIZ$ supports = "False"
+ */
 #define CONFIG_SER_HWHANDSHAKE   0
 
-/// Default baud rate (set to 0 to disable). $WIZ$ type = "boolean"
-#define CONFIG_SER_DEFBAUDRATE   0
-
-/// Enable ser_gets() and ser_gets_echo(). $WIZ$ type = "boolean"
-#define CONFIG_SER_GETS          0
-
-/// Enable second serial port in emulator. $WIZ$ type = "boolean"
-#define CONFIG_EMUL_UART1        0
+/**
+ * Default baudrate for all serial ports (set to 0 to disable).
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 0
+ */
+#define CONFIG_SER_DEFBAUDRATE   0UL
 
-/// For serial debug. $WIZ$ type = "boolean"
+/// Enable strobe pin for debugging serial interrupt. $WIZ$ type = "boolean"
 #define CONFIG_SER_STROBE        0
 
 #endif /* CFG_SER_H */