X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcfg%2Fcfg_ser.h;h=ec113e528bdf521b7468a0f8fb6129544ed6ac37;hb=57fa5e371a8b40afc99b922731b77d17c55330a4;hp=6af37794f1accaecacf96ae495d892cb9ed9c003;hpb=10d4559ee8860b118a0f6d285b29ffcc28760207;p=bertos.git

diff --git a/bertos/cfg/cfg_ser.h b/bertos/cfg/cfg_ser.h
index 6af37794..ec113e52 100644
--- a/bertos/cfg/cfg_ser.h
+++ b/bertos/cfg/cfg_ser.h
@@ -32,8 +32,6 @@
  *
  * \brief Configuration file for serial module.
  *
- * \version $Id$
- *
  * \author Daniele Basile <asterix@develer.com>
  */
 
@@ -46,98 +44,298 @@
  * Edit these define for your project.
  */
 
-/// Serial port settings. $WIZARD = { "type" : "int" }
-#define CONFIG_SER_PORT      0
-/// Serial port baudrate. $WIZARD = { "type" : "int" }
-#define CONFIG_SER_BAUDRATE  115200UL
-
-/// Spi port settings. $WIZARD = { "type" : "int" }
-#define CONFIG_SPI_PORT      0
-/// Spi port baudrate. $WIZARD = { "type" : "int" }
-#define CONFIG_SPI_BAUDRATE  5000000UL
-
+/**
+ * Enable port 0
+ * $WIZ$ type = "boolean"
+ * $WIZ$ supports = "xmega"
+ */
+#define CONFIG_UART0_ENABLED 1
 
-/// [bytes] Size of the outbound FIFO buffer for port 0. $WIZARD = { "type" : "int" }
+/**
+ * Size of the outbound FIFO buffer for port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ */
 #define CONFIG_UART0_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 0. $WIZARD = { "type" : "int" }
+/**
+ * Size of the inbound FIFO buffer for port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ */
 #define CONFIG_UART0_RXBUFSIZE  32
 
-/// [bytes] Size of the outbound FIFO buffer for port 1. $WIZARD = { "type" : "int" }
+/**
+ * Enable port 1
+ * $WIZ$ type = "boolean"
+ * $WIZ$ supports = "xmega"
+ */
+#define CONFIG_UART1_ENABLED 1
+
+/**
+ * Size of the outbound FIFO buffer for port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2 or xmega or (at91 and not atmega8 and not atmega168 and not atmega32)"
+ */
 #define CONFIG_UART1_TXBUFSIZE  32
 
-/// [bytes] Size of the inbound FIFO buffer for port 1. $WIZARD = { "type" : "int" }
+/**
+ * Size of the inbound FIFO buffer for port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2 or xmega or (at91 and not atmega8 and not atmega168 and not atmega32)"
+ */
 #define CONFIG_UART1_RXBUFSIZE  32
 
+/**
+ * Enable port 2
+ * $WIZ$ type = "boolean"
+ * $WIZ$ supports = "xmega and (not xmegad4)"
+ */
+#define CONFIG_UART2_ENABLED 1
+
+/**
+ * Size of the outbound FIFO buffer for port 2 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2 or (xmega and not xmegad4)"
+ */
+#define CONFIG_UART2_TXBUFSIZE  32
+
+/**
+ * Size of the inbound FIFO buffer for port 2 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lm3s or lpc2 or (xmega and not xmegad4)"
+ */
+#define CONFIG_UART2_RXBUFSIZE  32
+
+/**
+ * Enable port 3
+ * $WIZ$ type = "boolean"
+ * $WIZ$ supports = "xmega and not xmegad4"
+ */
+#define CONFIG_UART3_ENABLED 1
+
+/**
+ * Size of the outbound FIFO buffer for port 3 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lpc2 or xmega and not xmegad4"
+ */
+#define CONFIG_UART3_TXBUFSIZE  32
+
+/**
+ * Size of the inbound FIFO buffer for port 3 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "lpc2 or xmega and not xmegad4"
+ */
+#define CONFIG_UART3_RXBUFSIZE  32
+
+/**
+ * Enable port 4
+ * $WIZ$ type = "boolean"
+ * $WIZ$ supports = "xmega and not xmegad4"
+ */
+#define CONFIG_UART4_ENABLED 1
+
+/**
+ * Size of the outbound FIFO buffer for port 4 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "xmega and not xmegad4"
+ */
+#define CONFIG_UART4_TXBUFSIZE  32
+
+/**
+ * Size of the inbound FIFO buffer for port 4 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "xmega and not xmegad4"
+ */
+#define CONFIG_UART4_RXBUFSIZE  32
+
+/**
+ * Enable port 5
+ * $WIZ$ type = "boolean"
+ * $WIZ$ supports = "xmegaa1 or xmegaa3"
+ */
+#define CONFIG_UART5_ENABLED 1
+
+/**
+ * Size of the outbound FIFO buffer for port 5 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "xmegaa1 or xmegaa3"
+ */
+#define CONFIG_UART5_TXBUFSIZE  32
+
+/**
+ * Size of the inbound FIFO buffer for port 5 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "xmegaa1 or xmegaa3"
+ */
+#define CONFIG_UART5_RXBUFSIZE  32
+
+/**
+ * Enable port 6
+ * $WIZ$ type = "boolean"
+ * $WIZ$ supports = "xmegaa1 or xmegaa3"
+ */
+#define CONFIG_UART6_ENABLED 1
+
+/**
+ * Size of the outbound FIFO buffer for port 6 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "xmegaa1 or xmegaa3"
+ */
+#define CONFIG_UART6_TXBUFSIZE  32
+
+/**
+ * Size of the inbound FIFO buffer for port 6 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "xmegaa1 or xmegaa3"
+ */
+#define CONFIG_UART6_RXBUFSIZE  32
+
+/**
+ * Enable port 7
+ * $WIZ$ type = "boolean"
+ * $WIZ$ supports = "xmegaa1"
+ */
+#define CONFIG_UART7_ENABLED 1
+
+/**
+ * Size of the outbound FIFO buffer for port 7 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "xmegaa1"
+ */
+#define CONFIG_UART7_TXBUFSIZE  32
+
+/**
+ * Size of the inbound FIFO buffer for port 7 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "xmegaa1"
+ */
+#define CONFIG_UART7_RXBUFSIZE  32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port (AVR only). $WIZARD = { "type" : "int" }
+/**
+ * Size of the outbound FIFO buffer for SPI port [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "avr and not xmega"
+ */
 #define CONFIG_SPI_TXBUFSIZE    32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port (AVR only). $WIZARD = { "type" : "int" }
+/**
+ * Size of the inbound FIFO buffer for SPI port [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "avr and not xmega"
+ */
 #define CONFIG_SPI_RXBUFSIZE    32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 0. $WIZARD = { "type" : "int" }
+/**
+ * Size of the outbound FIFO buffer for SPI port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "at91"
+ */
 #define CONFIG_SPI0_TXBUFSIZE	32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 0. $WIZARD = { "type" : "int" }
+/**
+ * Size of the inbound FIFO buffer for SPI port 0 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "at91"
+ */
 #define CONFIG_SPI0_RXBUFSIZE	32
 
-/// [bytes] Size of the outbound FIFO buffer for SPI port 1. $WIZARD = { "type" : "int" }
+/**
+ * Size of the outbound FIFO buffer for SPI port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "at91"
+ */
 #define CONFIG_SPI1_TXBUFSIZE	32
 
-/// [bytes] Size of the inbound FIFO buffer for SPI port 1. $WIZARD = { "type" : "int" }
+/**
+ * Size of the inbound FIFO buffer for SPI port 1 [bytes].
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 2
+ * $WIZ$ supports = "at91"
+ */
 #define CONFIG_SPI1_RXBUFSIZE	32
 
 /**
- * SPI data order (AVR only).
+ * SPI data order.
  *
- * $WIZARD = {
- * "type" : "enum",
- * "value_list" : "ser_order_bit"
- * }
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "ser_order_bit"
+ * $WIZ$ supports = "avr and not xmega"
  */
 #define CONFIG_SPI_DATA_ORDER	SER_MSB_FIRST
 
-/// SPI clock division factor (AVR only). $WIZARD = { "type" : "int" }
+/**
+ * SPI clock division factor.
+ * $WIZ$ type = "int"
+ * $WIZ$ supports = "avr and not xmega"
+ */
 #define CONFIG_SPI_CLOCK_DIV	16
+
 /**
- * SPI clock polarity: normal low or normal high (AVR only).
- * $WIZARD = {
- * "type" : "enum",
- * "value_list" : "ser_spi_pol"
- * }
+ * SPI clock polarity: normal low or normal high.
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "ser_spi_pol"
+ * $WIZ$ supports = "avr and not xmega"
  */
 #define CONFIG_SPI_CLOCK_POL        SPI_NORMAL_LOW
 
 /**
  * SPI clock phase you can choose sample on first edge or
- * sample on second clock edge (AVR only)
- * $WIZARD = {
- * "type" : "enum",
- * "value_list" : "ser_spi_phase"
- * }
+ * sample on second clock edge.
+ * $WIZ$ type = "enum"
+ * $WIZ$ value_list = "ser_spi_phase"
+ * $WIZ$ supports = "avr and not xmega"
  */
 #define CONFIG_SPI_CLOCK_PHASE	    SPI_SAMPLE_ON_FIRST_EDGE
 
-/// Default transmit timeout (ms). Set to -1 to disable timeout support. $WIZARD = { "type" : "int" }
+/**
+ * Default transmit timeout (ms). Set to -1 to disable timeout support.
+ * $WIZ$ type = "int"
+ * $WIZ$ min = -1
+ */
 #define CONFIG_SER_TXTIMEOUT    -1
 
-/// Default receive timeout (ms). Set to -1 to disable timeout support. $WIZARD = { "type" : "int" }
+/**
+ * Default receive timeout (ms). Set to -1 to disable timeout support.
+ * $WIZ$ type = "int"
+ * $WIZ$ min = -1
+ */
 #define CONFIG_SER_RXTIMEOUT    -1
 
-/// Use RTS/CTS handshake. $WIZARD = { "type" : "boolean" }
+/**
+ * Use RTS/CTS handshake.
+ * $WIZ$ type = "boolean"
+ * $WIZ$ supports = "False"
+ */
 #define CONFIG_SER_HWHANDSHAKE   0
 
-/// Default baud rate (set to 0 to disable). $WIZARD = { "type" : "boolean" }
-#define CONFIG_SER_DEFBAUDRATE   0
-
-/// Enable ser_gets() and ser_gets_echo(). $WIZARD = { "type" : "boolean" }
-#define CONFIG_SER_GETS          0
-
-/// Enable second serial port in emulator. $WIZARD = { "type" : "boolean" }
-#define CONFIG_EMUL_UART1        0
+/**
+ * Default baudrate for all serial ports (set to 0 to disable).
+ * $WIZ$ type = "int"
+ * $WIZ$ min = 0
+ */
+#define CONFIG_SER_DEFBAUDRATE   0UL
 
-/// For serial debug. $WIZARD = { "type" : "boolean" }
+/// Enable strobe pin for debugging serial interrupt. $WIZ$ type = "boolean"
 #define CONFIG_SER_STROBE        0
 
 #endif /* CFG_SER_H */