X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Farm%2Fdrv%2Fadc_at91.c;h=66d0bde9c2335c66417e1d6b25d888c2171ede8e;hb=ab40eaf9ac5b43e7087588fe7f435bdbc9a6eb23;hp=b385184ea7c4a3fd9a442143ce9d726155698b36;hpb=92d5e5f668bb596036e7c4fe674b29448f7ac65d;p=bertos.git

diff --git a/bertos/cpu/arm/drv/adc_at91.c b/bertos/cpu/arm/drv/adc_at91.c
index b385184e..66d0bde9 100644
--- a/bertos/cpu/arm/drv/adc_at91.c
+++ b/bertos/cpu/arm/drv/adc_at91.c
@@ -40,15 +40,17 @@
  * whit a loop the finishing of conversion.
  *
  *
- * \version $Id$
  * \author Daniele Basile <asterix@develer.com>
  */
 
 
 #include "adc_at91.h"
 
+#include <cpu/irq.h>
+
 #include "cfg/cfg_adc.h"
-#include "cfg/cfg_kern.h"
+#include "cfg/cfg_proc.h"
+#include "cfg/cfg_signal.h"
 #include <cfg/macros.h>
 #include <cfg/compiler.h>
 
@@ -81,9 +83,9 @@
 	 * ADC ISR.
 	 * Simply signal the adc process that convertion is complete.
 	 */
-	static void ISR_FUNC adc_conversion_end_irq(void)
+	static DECLARE_ISR(adc_conversion_end_irq)
 	{
-		sig_signal(adc_process, SIG_ADC_COMPLETE);
+		sig_post(adc_process, SIG_ADC_COMPLETE);
 
 		/* Inform hw that we have served the IRQ */
 		AIC_EOICR = 0;
@@ -111,7 +113,7 @@
  * Select mux channel \a ch.
  * \todo only first 8 channels are selectable!
  */
-INLINE void adc_hw_select_ch(uint8_t ch)
+void adc_hw_select_ch(uint8_t ch)
 {
 	//Disable all channels
 	ADC_CHDR = ADC_CH_MASK;
@@ -123,13 +125,13 @@ INLINE void adc_hw_select_ch(uint8_t ch)
 /**
  * Start an ADC convertion.
  * If a kernel is present, preempt until convertion is complete, otherwise
- * a busy wait on ADCS bit is done.
+ * a busy wait on ADC_DRDY bit is done.
  */
-INLINE uint16_t adc_hw_read(void)
+uint16_t adc_hw_read(void)
 {
-	ASSERT(!(ADC_SR & ADC_EOC_MASK));
-
 	#if CONFIG_KERN
+		/* Ensure ADC is not already in use by another process */
+		ASSERT(adc_process == NULL);
 		adc_process = proc_current();
 	#endif
 
@@ -138,21 +140,27 @@ INLINE uint16_t adc_hw_read(void)
 
 	#if CONFIG_KERN
 		// Ensure IRQs enabled.
-		ASSERT(IRQ_ENABLED());
+		IRQ_ASSERT_ENABLED();
 		sig_wait(SIG_ADC_COMPLETE);
+
+		/* Prevent race condition in case of preemptive kernel */
+		uint16_t ret = ADC_LCDR;
+		MEMORY_BARRIER;
+		adc_process = NULL;
+		return ret;
 	#else
 		//Wait in polling until is done
 		while (!(ADC_SR & BV(ADC_DRDY)));
-	#endif
 
-	//Return the last converted data
-	return(ADC_LCDR);
+		//Return the last converted data
+		return(ADC_LCDR);
+	#endif
 }
 
 /**
  * Init ADC hardware.
  */
-INLINE void adc_hw_init(void)
+void adc_hw_init(void)
 {
 	//Init ADC pins.
 	ADC_INIT_PINS();
@@ -175,6 +183,7 @@ INLINE void adc_hw_init(void)
 	#endif
 	/* \} */
 
+	LOG_INFO("Computed ADC_CLOCK %ld\n", ADC_COMPUTED_CLOCK);
 	LOG_INFO("prescaler[%ld], stup[%ld], shtim[%ld]\n",ADC_COMPUTED_PRESCALER, ADC_COMPUTED_STARTUPTIME,  ADC_COMPUTED_SHTIME);