X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Farm%2Fdrv%2Fflash_at91.c;h=b20d11313526ba7ae4a84c2f29273b442063641b;hb=2db7ecba815ec3054934fe1ea99dac3241391204;hp=06ff71e4dbb77503ee9842dfbdc2087ced723272;hpb=1ddc1613b03c97b8ef84c4657c5fbc82e86fa32b;p=bertos.git

diff --git a/bertos/cpu/arm/drv/flash_at91.c b/bertos/cpu/arm/drv/flash_at91.c
index 06ff71e4..b20d1131 100644
--- a/bertos/cpu/arm/drv/flash_at91.c
+++ b/bertos/cpu/arm/drv/flash_at91.c
@@ -346,33 +346,4 @@ void flash_hw_init(struct Flash *fd)
 	fd->fd.flush = flash_at91_kfileFlush;
 
 	flash_at91_open(fd);
-
-	uint32_t fmcn;
-	uint32_t fws = 0;
-
-
-	/*
-	 * Compute values to insert into mode register.
-	 */
-
-	/* main clocks in 1.5uS */
-	fmcn = (CPU_FREQ/1000000ul) + (CPU_FREQ/2000000ul) + 1;
-
-	/* hard overclocking */
-	if (fmcn > 0xFF)
-		fmcn = 0xFF;
-
-	/* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */
-	if (CPU_FREQ <= 33333ul)
-		fmcn = 0;
-
-	/* Only allow fws=0 if clock frequency is < 30 MHz. */
-	if (CPU_FREQ > 30000000ul)
-	{
-		fws = 1;
-	}
-
-	// Set wait states and number of MCK cycles in 1.5 usecs
-	MC_FMR = fmcn << 16 | fws << 8;
-
 }