X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Farm%2Fhw%2Fcrtat91sam7_rom.S;h=51635fde4cb36b16a6ff32297bfea069d8989182;hb=3a982dd4047b2cfe48c339d225813b95883ed19c;hp=0282785dd8a94c800c6239b7575dc346543a2790;hpb=b46f64914c62fbb0297728280478681659469654;p=bertos.git

diff --git a/bertos/cpu/arm/hw/crtat91sam7_rom.S b/bertos/cpu/arm/hw/crtat91sam7_rom.S
index 0282785d..51635fde 100644
--- a/bertos/cpu/arm/hw/crtat91sam7_rom.S
+++ b/bertos/cpu/arm/hw/crtat91sam7_rom.S
@@ -73,18 +73,18 @@
 #include "cfg/cfg_arch.h"
 
 
-#if CPU_FREQ != 48023000L
+#if CPU_FREQ != 48054857L
 	/* Avoid errors on nightly test */
 	#if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
-		#warning Clock registers set for 48.023MHz operation, revise following code if you want a different clock.
+		#warning Clock registers set for 48.055MHz operation, revise following code if you want a different clock.
 	#endif
 #endif
 
 
 #if CPU_ARM_SAM7S_LARGE || CPU_ARM_SAM7X
 	/*
-	 * With a 18.420MHz cristal, master clock is:
-	 * (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
+	 * With a 18.432MHz cristal, master clock is:
+	 * (((18.432 * (PLL_MUL_VAL + 1)) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.055MHz
 	 */
 	#define PLL_MUL_VAL  72  /**< Real multiplier value is PLL_MUL_VAL + 1! */
 	#define PLL_DIV_VAL  14