X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Farm%2Fhw%2Fcrtat91sam7_rom.S;h=c7706d73ffbaa9135af0751d6e7c4d67ec47b3d1;hb=00455e9ad45329213214919462b4bf1e9cde6f11;hp=0a2fa4a791be63a6c3fbe0b246cb1bb6c756654a;hpb=345f93de1963f49bdb194d2b06c8c5d7ba0a3e5f;p=bertos.git

diff --git a/bertos/cpu/arm/hw/crtat91sam7_rom.S b/bertos/cpu/arm/hw/crtat91sam7_rom.S
index 0a2fa4a7..c7706d73 100644
--- a/bertos/cpu/arm/hw/crtat91sam7_rom.S
+++ b/bertos/cpu/arm/hw/crtat91sam7_rom.S
@@ -70,7 +70,7 @@
  *
  */
 
-#include "hw_cpu.h"
+#include "hw/hw_cpu.h"
 #include <cpu/detect.h>
 
 
@@ -79,7 +79,7 @@
 #endif
 
 
-#if CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256
+#if CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
 	/**
 	* With a 18.420MHz cristal, master clock is:
 	* (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
@@ -110,7 +110,9 @@
 	#define PMC_MOSCS             (1 << 0)
 	#define PMC_LOCK              (1 << 2)
 	#define PMC_MCKRDY            (1 << 3)
+	#define PMC_CSS_MASK        0x00000003
 	#define PMC_CSS_PLL_CLK     0x00000003
+	#define PMC_PRES_MASK       0x0000001C
 	#define PMC_PRES_CLK_2      0x00000004
 
 	#define CKGR_MOR_OFF        0x00000020
@@ -228,6 +230,28 @@ wait_moscs:
         tst     r0, #PMC_MOSCS
         beq     wait_moscs
 
+        /*
+         * Switch to Slow oscillator clock.
+         */
+        ldr     r0, [r1, #PMC_MCKR_OFF]
+        and     r0, r0, #~PMC_CSS_MASK
+        str     r0, [r1, #PMC_MCKR_OFF]
+wait_slowosc:
+        ldr     r0, [r1, #PMC_SR_OFF]
+        tst     r0, #PMC_MCKRDY
+        beq     wait_slowosc
+
+        /*
+         * Switch to prescaler div 1 factor.
+         */
+        ldr     r0, [r1, #PMC_MCKR_OFF]
+        and     r0, r0, #~PMC_PRES_MASK
+        str     r0, [r1, #PMC_MCKR_OFF]
+wait_presc:
+        ldr     r0, [r1, #PMC_SR_OFF]
+        tst     r0, #PMC_MCKRDY
+        beq     wait_presc
+
         /*
          * Set PLL:
          * PLLfreq = crystal / divider * (multiplier + 1)