X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Farm%2Fhw%2Finit_lpc2.c;h=033216d1d93540be4ea4430367c003c2f5022e38;hb=d57ed7ecf592540f90a714813bd5619cac825306;hp=7e03bf6ef358b4950d50db10ff72e00d18039b40;hpb=3d80d429ffc2ba832bc829c761c577b3693b1fa6;p=bertos.git

diff --git a/bertos/cpu/arm/hw/init_lpc2.c b/bertos/cpu/arm/hw/init_lpc2.c
index 7e03bf6e..033216d1 100644
--- a/bertos/cpu/arm/hw/init_lpc2.c
+++ b/bertos/cpu/arm/hw/init_lpc2.c
@@ -33,11 +33,12 @@
  * \author Francesco Sacchi <batt@develer.com>
  *
  * \brief LPC2378 CRT.
- */
-#include <cpu/irq.h>
-
-#include <io/lpc23xx.h>
-
+ * notest:arm
+ */
+#include <cpu/irq.h>
+#include <drv/vic_lpc2.h>
+#include <io/lpc23xx.h>
+
 #if CPU_FREQ != 72000000UL
 	/* Avoid errors on nightly test */
 	#if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
@@ -52,70 +53,77 @@
 #define PLL_MUL_VAL  11
 #define PLL_DIV_VAL  0
 #define LPC2_CPUCLOCK_DIV 3
-
-
-/* PLL feed sequence */
-#define PLL_FEED_SEQ() ATOMIC(PLLFEED = 0xAA; PLLFEED = 0x55;)
-
-static void configurePll(void)
-{
-	/* Disconnect and disable the PLL, if already active */
-	if (PLLSTAT & (1 << 25))
-	{
-		/* Disconnect PLL, but leave it enabled */
-		PLLCON = 0x01;
-		PLL_FEED_SEQ();
-		/* Disable PLL */
-		PLLCON = 0;
-		PLL_FEED_SEQ();
-	}
-
-	/* Enable the main oscillator and wait for it to be stable */
-	SCS |= (1 << 5);
-    while (!(SCS & (1 << 6))) ;
-
-	/* Select the main oscillator as the PLL clock source */
-	CLKSRCSEL = 0x01;
-
-	/* Set up PLL mul and div */
-	PLLCFG = PLL_MUL_VAL | (PLL_DIV_VAL << 16);
-	PLL_FEED_SEQ();
-	
-	/* Enable PLL, disconnected */
-	PLLCON = 0x01;
-	PLL_FEED_SEQ();
-
-	/* Set clock divider */
-	CCLKCFG = LPC2_CPUCLOCK_DIV;
-
-	/* Wait for the PLL to lock */
-	while (!(PLLSTAT & (1 << 26))) ;
-    
-	/* Enable and connect the PLL */
-    PLLCON = 0x03;
-	PLL_FEED_SEQ();
-}
-
-void __init1(void);
-
-void __init1(void)
-{
-	/* Map irq vectors to internal flash */
-	MEMMAP = 0x01;
-	/* Configure PLL, switch from IRC to Main OSC */
-	configurePll();
-
-	/* Set memory accelerator module flash timings */
-#if CPU_FREQ < 20000000UL
-	MAMTIM = 1;
-#elif CPU_FREQ < 40000000UL
-	MAMTIM = 2;
-#elif CPU_FREQ < 60000000UL
-	MAMTIM = 3;
-#else
-	MAMTIM = 4;
-#endif
-	
-	/* Memory accelerator module fully enabled */
-	MAMCR = 0x02;
-}
+
+
+/* PLL feed sequence */
+#define PLL_FEED_SEQ() ATOMIC(PLLFEED = 0xAA; PLLFEED = 0x55;)
+
+static void configurePll(void)
+{
+	/* Disconnect and disable the PLL, if already active */
+	if (PLLSTAT & (1 << 25))
+	{
+		/* Disconnect PLL, but leave it enabled */
+		PLLCON = 0x01;
+		PLL_FEED_SEQ();
+		/* Disable PLL */
+		PLLCON = 0;
+		PLL_FEED_SEQ();
+	}
+
+	/* Enable the main oscillator and wait for it to be stable */
+	SCS |= (1 << 5);
+    while (!(SCS & (1 << 6))) ;
+
+	/* Select the main oscillator as the PLL clock source */
+	CLKSRCSEL = 0x01;
+
+	/* Set up PLL mul and div */
+	PLLCFG = PLL_MUL_VAL | (PLL_DIV_VAL << 16);
+	PLL_FEED_SEQ();
+	
+	/* Enable PLL, disconnected */
+	PLLCON = 0x01;
+	PLL_FEED_SEQ();
+
+	/* Set clock divider */
+	CCLKCFG = LPC2_CPUCLOCK_DIV;
+
+	/* Wait for the PLL to lock */
+	while (!(PLLSTAT & (1 << 26))) ;
+    
+	/* Enable and connect the PLL */
+    PLLCON = 0x03;
+	PLL_FEED_SEQ();
+}
+
+void __init1(void);
+
+void __init1(void)
+{
+	/* Map irq vectors to internal flash */
+	MEMMAP = 0x01;
+	/* Configure PLL, switch from IRC to Main OSC */
+	configurePll();
+
+	/* Set memory accelerator module flash timings */
+#if CPU_FREQ < 20000000UL
+	MAMTIM = 1;
+#elif CPU_FREQ < 40000000UL
+	MAMTIM = 2;
+#elif CPU_FREQ < 60000000UL
+	MAMTIM = 3;
+#else
+	MAMTIM = 4;
+#endif
+	
+	/* Memory accelerator module fully enabled */
+	MAMCR = 0x02;
+}
+
+void __init2(void);
+
+void __init2(void)
+{
+	vic_init();
+}