X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Farm%2Fio%2Fat91_spi.h;h=fd6bb7466a5fcb5d37317c042763cd2985d85353;hb=4908f97f870e5f474c845a4f7e7c2f7d91c236b4;hp=4766b75d4d4a578fc5d77f3d28f9dd264ab8f4c4;hpb=345f93de1963f49bdb194d2b06c8c5d7ba0a3e5f;p=bertos.git

diff --git a/bertos/cpu/arm/io/at91_spi.h b/bertos/cpu/arm/io/at91_spi.h
index 4766b75d..fd6bb746 100644
--- a/bertos/cpu/arm/io/at91_spi.h
+++ b/bertos/cpu/arm/io/at91_spi.h
@@ -233,16 +233,16 @@
 	#define SPI0_CSR2	(*((reg32_t *)(SPI0_BASE + SPI_CSR2_OFF)))      ///< SPI Chip Select Register 2 Read/Write Reset=0x0.
 	#define SPI0_CSR3	(*((reg32_t *)(SPI0_BASE + SPI_CSR3_OFF)))      ///< SPI Chip Select Register 3 Read/Write Reset=0x0.
 	#if defined(SPI_HAS_PDC)
-		#define SPI0_RPR    (*((reg32_t *)(SPI0_BASE + PERIPH_RPR_OFF))    ///< PDC channel 0 receive pointer register.
-		#define SPI0_RCR    (*((reg32_t *)(SPI0_BASE + PERIPH_RCR_OFF))    ///< PDC channel 0 receive counter register.
-		#define SPI0_TPR    (*((reg32_t *)(SPI0_BASE + PERIPH_TPR_OFF))    ///< PDC channel 0 transmit pointer register.
-		#define SPI0_TCR    (*((reg32_t *)(SPI0_BASE + PERIPH_TCR_OFF))    ///< PDC channel 0 transmit counter register.
-		#define SPI0_RNPR   (*((reg32_t *)(SPI0_BASE + PERIPH_RNPR_OFF))   ///< PDC channel 0 receive next pointer register.
-		#define SPI0_RNCR   (*((reg32_t *)(SPI0_BASE + PERIPH_RNCR_OFF))   ///< PDC channel 0 receive next counter register.
-		#define SPI0_TNPR   (*((reg32_t *)(SPI0_BASE + PERIPH_TNPR_OFF))   ///< PDC channel 0 transmit next pointer register.
-		#define SPI0_TNCR   (*((reg32_t *)(SPI0_BASE + PERIPH_TNCR_OFF))   ///< PDC channel 0 transmit next counter register.
-		#define SPI0_PTCR   (*((reg32_t *)(SPI0_BASE + PERIPH_PTCR_OFF))   ///< PDC channel 0 transfer control register.
-		#define SPI0_PTSR   (*((reg32_t *)(SPI0_BASE + PERIPH_PTSR_OFF))   ///< PDC channel 0 transfer status register.
+		#define SPI0_RPR    (*((reg32_t *)(SPI0_BASE + PERIPH_RPR_OFF)))    ///< PDC channel 0 receive pointer register.
+		#define SPI0_RCR    (*((reg32_t *)(SPI0_BASE + PERIPH_RCR_OFF)))    ///< PDC channel 0 receive counter register.
+		#define SPI0_TPR    (*((reg32_t *)(SPI0_BASE + PERIPH_TPR_OFF)))    ///< PDC channel 0 transmit pointer register.
+		#define SPI0_TCR    (*((reg32_t *)(SPI0_BASE + PERIPH_TCR_OFF)))    ///< PDC channel 0 transmit counter register.
+		#define SPI0_RNPR   (*((reg32_t *)(SPI0_BASE + PERIPH_RNPR_OFF)))   ///< PDC channel 0 receive next pointer register.
+		#define SPI0_RNCR   (*((reg32_t *)(SPI0_BASE + PERIPH_RNCR_OFF)))   ///< PDC channel 0 receive next counter register.
+		#define SPI0_TNPR   (*((reg32_t *)(SPI0_BASE + PERIPH_TNPR_OFF)))   ///< PDC channel 0 transmit next pointer register.
+		#define SPI0_TNCR   (*((reg32_t *)(SPI0_BASE + PERIPH_TNCR_OFF)))   ///< PDC channel 0 transmit next counter register.
+		#define SPI0_PTCR   (*((reg32_t *)(SPI0_BASE + PERIPH_PTCR_OFF)))   ///< PDC channel 0 transfer control register.
+		#define SPI0_PTSR   (*((reg32_t *)(SPI0_BASE + PERIPH_PTSR_OFF)))   ///< PDC channel 0 transfer status register.
 	#endif /* SPI_HAS_PDC */
 #endif /* SPI0_BASE */
 /*\}*/