X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Farm%2Fio%2Fat91sam7.h;h=2783307faf27bf130e85c351eb57687c5d582c42;hb=507e95236d43b2aa6d6b6e46bde5cb92345ab034;hp=712344b9910d1082e27d857e8d3f1a4cdc01bcbc;hpb=afd2885238f50fa9b96d05aa3fa5f88706440561;p=bertos.git

diff --git a/bertos/cpu/arm/io/at91sam7.h b/bertos/cpu/arm/io/at91sam7.h
index 712344b9..2783307f 100644
--- a/bertos/cpu/arm/io/at91sam7.h
+++ b/bertos/cpu/arm/io/at91sam7.h
@@ -76,7 +76,7 @@
 
 #include <cfg/compiler.h>
 
-#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7S256
+#if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE
 	#define FLASH_BASE      0x100000UL
 	#define RAM_BASE        0x200000UL
 
@@ -100,7 +100,7 @@
 	#define VREG_BASE       0xFFFFFD60      ///< Voltage regulator mode controller base address.
 	#define MC_BASE         0xFFFFFF00      ///< Memory controller base.
 
-	#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+	#if CPU_ARM_SAM7X
 		#define CAN_BASE        0xFFFD0000      ///< PWM controller base address.
 		#define EMAC_BASE       0xFFFDC000      ///< Ethernet MAC address.
 		#define SPI0_BASE       0xFFFE0000      ///< SPI0 base address.
@@ -108,7 +108,7 @@
 		#define PIOB_BASE       0xFFFFF600      ///< PIO base address.
 	#endif
 
-	#if CPU_ARM_AT91SAM7S256
+	#if CPU_ARM_SAM7S_LARGE
 		#define SPI_BASE        0xFFFE0000      ///< SPI0 base address.
 	#endif
 
@@ -122,9 +122,37 @@
 	#define SSC_HAS_PDC                1
 	#define USART_HAS_PDC              1
 
+	/* PDC registers */
+	#define PERIPH_RPR_OFF  0x100  ///< Receive Pointer Register.
+	#define PERIPH_RCR_OFF  0x104  ///< Receive Counter Register.
+	#define PERIPH_TPR_OFF  0x108  ///< Transmit Pointer Register.
+	#define PERIPH_TCR_OFF  0x10C  ///< Transmit Counter Register.
+	#define PERIPH_RNPR_OFF 0x110  ///< Receive Next Pointer Register.
+	#define PERIPH_RNCR_OFF 0x114  ///< Receive Next Counter Register.
+	#define PERIPH_TNPR_OFF 0x118  ///< Transmit Next Pointer Register.
+	#define PERIPH_TNCR_OFF 0x11C  ///< Transmit Next Counter Register.
+	#define PERIPH_PTCR_OFF 0x120  ///< PDC Transfer Control Register.
+	#define PERIPH_PTSR_OFF 0x124  ///< PDC Transfer Status Register.
+
+	#define PDC_RXTEN  0
+	#define PDC_RXTDIS 1
+	#define PDC_TXTEN  8
+	#define PDC_TXTDIS 9
+
 #else
-	#error No base addrese register definition for selected ARM CPU
+	#error No base address register definition for selected ARM CPU
+
+#endif
 
+#if CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256
+	#define FLASH_MEM_SIZE          0x40000UL ///< Internal flash memory size
+	#define FLASH_PAGE_SIZE_BYTES         256 ///< Size of cpu flash memory page in bytes
+	#define FLASH_BANKS_NUM                 1 ///< Number of flash banks
+	#define FLASH_SECTORS_NUM              16 ///< Number of flash sector
+	#define FLASH_PAGE_PER_SECTOR          64 ///< Number of page for sector
+
+#else
+	#error Memory size definition for selected ARM CPU
 #endif
 
 #include "at91_aic.h"
@@ -141,13 +169,14 @@
 #include "at91_pwm.h"
 #include "at91_spi.h"
 #include "at91_twi.h"
+#include "at91_ssc.h"
 //TODO: add other peripherals
 
 /**
  * Peripheral Identifiers and Interrupts
  *\{
  */
-#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X128
+#if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE
 	#define FIQ_ID      0       ///< Fast interrupt ID.
 	#define SYSC_ID     1       ///< System controller interrupt.
 	#define US0_ID      6       ///< USART 0 ID.
@@ -163,7 +192,7 @@
 	#define IRQ0_ID     30      ///< External interrupt 0 ID.
 	#define IRQ1_ID     31      ///< External interrupt 1 ID.
 
-	#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+	#if CPU_ARM_SAM7X
 		#define PIOA_ID     2       ///< Parallel A I/O controller ID.
 		#define PIOB_ID     3       ///< Parallel B I/O controller ID.
 		#define SPI0_ID     4       ///< Serial peripheral interface 0 ID.
@@ -175,7 +204,7 @@
 
 	#endif
 
-	#if CPU_ARM_AT91SAM7S256
+	#if CPU_ARM_SAM7S_LARGE
 		#define PIOA_ID     2       ///< Parallel I/O controller ID.
 		/* ID 3 is reserved */
 		#define ADC_ID      4       ///< Analog to digital converter ID.
@@ -193,14 +222,14 @@
  * USART & DEBUG pin names
  *\{
  */
-#if CPU_ARM_AT91SAM7S256
+#if CPU_ARM_SAM7S_LARGE
 	#define RXD0        5
 	#define TXD0        6
 	#define RXD1       21
 	#define TXD1       22
 	#define DTXD       10
 	#define DRXD        9
-#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+#elif CPU_ARM_SAM7X
 	#define RXD0        0 // PA0
 	#define TXD0        1 // PA1
 	#define RXD1        5 // PA5
@@ -216,13 +245,13 @@
  * SPI pins name
  *\{
  */
-#if CPU_ARM_AT91SAM7S256
+#if CPU_ARM_SAM7S_LARGE
 	#define SPI0_NPCS0      11  // Same as NSS pin.
 	#define SPI0_MISO       12
 	#define SPI0_MOSI       13
 	#define SPI0_SPCK       14
 
-#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+#elif CPU_ARM_SAM7X
 	#define SPI0_NPCS0  12 // Same as NSS pin. PA12
 	#define SPI0_NPCS1  13 // PA13
 	#define SPI0_NPCS2  14 // PA14
@@ -245,11 +274,39 @@
 #endif
 /*\}*/
 
+/**
+ * SSC pins name
+ *\{
+ */
+#if CPU_ARM_SAM7S_LARGE
+
+	#define SSC_TF     15 // PA15
+	#define SSC_TK     16 // PA16
+	#define SSC_TD     17 // PA17
+	#define SSC_RD     18 // PA18
+	#define SSC_RK     19 // PA19
+	#define SSC_RF     20 // PA20
+
+#elif CPU_ARM_SAM7X
+
+	#define SSC_TF     21 // PA21
+	#define SSC_TK     22 // PA22
+	#define SSC_TD     23 // PA23
+	#define SSC_RD     24 // PA24
+	#define SSC_RK     25 // PA25
+	#define SSC_RF     26 // PA26
+
+#else
+	#error No SSC pins name definition for selected ARM CPU
+
+#endif
+/*\}*/
+
 /**
  * Timer counter pins definition.
  *\{
  */
-#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+#if CPU_ARM_SAM7X
 	#define TIOA0  23 // PB23
 	#define TIOB0  24 // PB24
 	#define TIOA1  25 // PB25
@@ -260,7 +317,7 @@
 	#define TIO_PIO_PDR     PIOB_PDR
 	#define TIO_PIO_ABSR    PIOB_ASR
 
-#elif CPU_ARM_AT91SAM7S256
+#elif CPU_ARM_SAM7S_LARGE
 	#define TIOA0  0 // PA0
 	#define TIOB0  1 // PA1
 	#define TIOA1  15 // PA15
@@ -272,7 +329,7 @@
 	#define TIO_PIO_ABSR    PIOA_BSR
 
 #else
-	#error No Timer Counter pins' names definition for selected ARM CPU
+	#error No Timer Counter names of pins definition for selected ARM CPU
 
 #endif
 /*\}*/
@@ -282,7 +339,7 @@
  * PWM pins definition.
  *\{
  */
-#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+#if CPU_ARM_SAM7X
 	#define PWM0  19 // PB19
 	#define PWM1  20 // PB20
 	#define PWM2  21 // PB21
@@ -294,7 +351,7 @@
 	#define PWM_PIO_OER     PIOB_OER
 	#define PWM_PIO_ABSR    PIOB_ASR
 
-#elif CPU_ARM_AT91SAM7S256
+#elif CPU_ARM_SAM7S_LARGE
 	#define PWM0  11 // PA11
 	#define PWM1  12 // PA12
 	#define PWM2  13 // PA13
@@ -307,7 +364,7 @@
 	#define PWM_PIO_ABSR    PIOA_BSR
 
 #else
-	#error No PWM pins' names definition for selected ARM CPU
+	#error No PWM names of pins definition for selected ARM CPU
 
 #endif
 /*\}*/
@@ -316,30 +373,30 @@
  * TWI pins definition.
  *\{
  */
-#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+#if CPU_ARM_SAM7X
 	#define TWD  10
 	#define TWCK 11
 
-#elif CPU_ARM_AT91SAM7S256
+#elif CPU_ARM_SAM7S_LARGE
 	#define TWD  3    //PA3
 	#define TWCK 4    //PA4
 
 #else
-	#error No TWI pins' names definition for selected ARM CPU
+	#error No TWI names of pins definition for selected ARM CPU
 #endif
 
 /**
  * ADC pins definition.
  *\{
  */
-#if CPU_ARM_AT91SAM7X256
+#if CPU_ARM_SAM7X
 	#define ADTRG   18 // PB18
 	#define AD0     23 // PB27
 	#define AD1     24 // PB28
 	#define AD2     25 // PB29
 	#define AD3     26 // PB30
 
-#elif CPU_ARM_AT91SAM7S256
+#elif CPU_ARM_SAM7S_LARGE
 	#define ADTRG   18 // PA8
 	#define AD0      0 // PA17
 	#define AD1      1 // PA18
@@ -347,7 +404,7 @@
 	#define AD3     16 // PA20
 
 #else
-	#error No ADC pins' names definition for selected ARM CPU
+	#error No ADC names of pins definition for selected ARM CPU
 
 #endif
 /*\}*/