X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Farm%2Fio%2Fat91sam7.h;h=6c645dcab9074958f9860044f8770453e9cc9558;hb=563795df4180aaceb7d69306551230c98fbca879;hp=e41ab1c54b78ed1eb73d4164128acff9a8ca9e0e;hpb=47c6faff7c70eed914055d97fc432b4066b8cd9b;p=bertos.git diff --git a/bertos/cpu/arm/io/at91sam7.h b/bertos/cpu/arm/io/at91sam7.h index e41ab1c5..6c645dca 100644 --- a/bertos/cpu/arm/io/at91sam7.h +++ b/bertos/cpu/arm/io/at91sam7.h @@ -30,7 +30,6 @@ * * --> * - * \version $Id$ * * \author Francesco Sacchi * \author Daniele Basile @@ -76,7 +75,7 @@ #include -#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7S256 +#if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE #define FLASH_BASE 0x100000UL #define RAM_BASE 0x200000UL @@ -100,7 +99,7 @@ #define VREG_BASE 0xFFFFFD60 ///< Voltage regulator mode controller base address. #define MC_BASE 0xFFFFFF00 ///< Memory controller base. - #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 + #if CPU_ARM_SAM7X #define CAN_BASE 0xFFFD0000 ///< PWM controller base address. #define EMAC_BASE 0xFFFDC000 ///< Ethernet MAC address. #define SPI0_BASE 0xFFFE0000 ///< SPI0 base address. @@ -108,7 +107,7 @@ #define PIOB_BASE 0xFFFFF600 ///< PIO base address. #endif - #if CPU_ARM_AT91SAM7S256 + #if CPU_ARM_SAM7S_LARGE #define SPI_BASE 0xFFFE0000 ///< SPI0 base address. #endif @@ -122,9 +121,58 @@ #define SSC_HAS_PDC 1 #define USART_HAS_PDC 1 + /* PDC registers */ + #define PERIPH_RPR_OFF 0x100 ///< Receive Pointer Register. + #define PERIPH_RCR_OFF 0x104 ///< Receive Counter Register. + #define PERIPH_TPR_OFF 0x108 ///< Transmit Pointer Register. + #define PERIPH_TCR_OFF 0x10C ///< Transmit Counter Register. + #define PERIPH_RNPR_OFF 0x110 ///< Receive Next Pointer Register. + #define PERIPH_RNCR_OFF 0x114 ///< Receive Next Counter Register. + #define PERIPH_TNPR_OFF 0x118 ///< Transmit Next Pointer Register. + #define PERIPH_TNCR_OFF 0x11C ///< Transmit Next Counter Register. + #define PERIPH_PTCR_OFF 0x120 ///< PDC Transfer Control Register. + #define PERIPH_PTSR_OFF 0x124 ///< PDC Transfer Status Register. + + #define PDC_RXTEN 0 + #define PDC_RXTDIS 1 + #define PDC_TXTEN 8 + #define PDC_TXTDIS 9 + #else - #error No base addrese register definition for selected ARM CPU + #error No base address register definition for selected ARM CPU + +#endif +#if CPU_ARM_AT91SAM7S64 + #define FLASH_MEM_SIZE 0x10000UL ///< Internal flash memory size + #define FLASH_PAGE_SIZE_BYTES 128 ///< Size of cpu flash memory page in bytes + #define FLASH_BANKS_NUM 1 ///< Number of flash banks + #define FLASH_SECTORS_NUM 16 ///< Number of flash sector + #define FLASH_PAGE_PER_SECTOR 32 ///< Number of page for sector + +#elif CPU_ARM_AT91SAM7S128 || CPU_ARM_AT91SAM7X128 + #define FLASH_MEM_SIZE 0x20000UL ///< Internal flash memory size + #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes + #define FLASH_BANKS_NUM 1 ///< Number of flash banks + #define FLASH_SECTORS_NUM 8 ///< Number of flash sector + #define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector + +#elif CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256 + #define FLASH_MEM_SIZE 0x40000UL ///< Internal flash memory size + #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes + #define FLASH_BANKS_NUM 1 ///< Number of flash banks + #define FLASH_SECTORS_NUM 16 ///< Number of flash sector + #define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector + +#elif CPU_ARM_AT91SAM7S512 || CPU_ARM_AT91SAM7X512 + #define FLASH_MEM_SIZE 0x80000UL ///< Internal flash memory size + #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes + #define FLASH_BANKS_NUM 2 ///< Number of flash banks + #define FLASH_SECTORS_NUM 32 ///< Number of flash sector + #define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector + +#else + #error Memory size definition for selected ARM CPU #endif #include "at91_aic.h" @@ -141,13 +189,15 @@ #include "at91_pwm.h" #include "at91_spi.h" #include "at91_twi.h" +#include "at91_ssc.h" +#include "at91_emac.h" //TODO: add other peripherals /** * Peripheral Identifiers and Interrupts *\{ */ -#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X128 +#if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE #define FIQ_ID 0 ///< Fast interrupt ID. #define SYSC_ID 1 ///< System controller interrupt. #define US0_ID 6 ///< USART 0 ID. @@ -163,7 +213,7 @@ #define IRQ0_ID 30 ///< External interrupt 0 ID. #define IRQ1_ID 31 ///< External interrupt 1 ID. - #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 + #if CPU_ARM_SAM7X #define PIOA_ID 2 ///< Parallel A I/O controller ID. #define PIOB_ID 3 ///< Parallel B I/O controller ID. #define SPI0_ID 4 ///< Serial peripheral interface 0 ID. @@ -175,7 +225,7 @@ #endif - #if CPU_ARM_AT91SAM7S256 + #if CPU_ARM_SAM7S_LARGE #define PIOA_ID 2 ///< Parallel I/O controller ID. /* ID 3 is reserved */ #define ADC_ID 4 ///< Analog to digital converter ID. @@ -193,14 +243,14 @@ * USART & DEBUG pin names *\{ */ -#if CPU_ARM_AT91SAM7S256 +#if CPU_ARM_SAM7S_LARGE #define RXD0 5 #define TXD0 6 #define RXD1 21 #define TXD1 22 #define DTXD 10 #define DRXD 9 -#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#elif CPU_ARM_SAM7X #define RXD0 0 // PA0 #define TXD0 1 // PA1 #define RXD1 5 // PA5 @@ -216,13 +266,13 @@ * SPI pins name *\{ */ -#if CPU_ARM_AT91SAM7S256 +#if CPU_ARM_SAM7S_LARGE #define SPI0_NPCS0 11 // Same as NSS pin. #define SPI0_MISO 12 #define SPI0_MOSI 13 #define SPI0_SPCK 14 -#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#elif CPU_ARM_SAM7X #define SPI0_NPCS0 12 // Same as NSS pin. PA12 #define SPI0_NPCS1 13 // PA13 #define SPI0_NPCS2 14 // PA14 @@ -245,11 +295,39 @@ #endif /*\}*/ +/** + * SSC pins name + *\{ + */ +#if CPU_ARM_SAM7S_LARGE + + #define SSC_TF 15 // PA15 + #define SSC_TK 16 // PA16 + #define SSC_TD 17 // PA17 + #define SSC_RD 18 // PA18 + #define SSC_RK 19 // PA19 + #define SSC_RF 20 // PA20 + +#elif CPU_ARM_SAM7X + + #define SSC_TF 21 // PA21 + #define SSC_TK 22 // PA22 + #define SSC_TD 23 // PA23 + #define SSC_RD 24 // PA24 + #define SSC_RK 25 // PA25 + #define SSC_RF 26 // PA26 + +#else + #error No SSC pins name definition for selected ARM CPU + +#endif +/*\}*/ + /** * Timer counter pins definition. *\{ */ -#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#if CPU_ARM_SAM7X #define TIOA0 23 // PB23 #define TIOB0 24 // PB24 #define TIOA1 25 // PB25 @@ -260,7 +338,7 @@ #define TIO_PIO_PDR PIOB_PDR #define TIO_PIO_ABSR PIOB_ASR -#elif CPU_ARM_AT91SAM7S256 +#elif CPU_ARM_SAM7S_LARGE #define TIOA0 0 // PA0 #define TIOB0 1 // PA1 #define TIOA1 15 // PA15 @@ -282,7 +360,7 @@ * PWM pins definition. *\{ */ -#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#if CPU_ARM_SAM7X #define PWM0 19 // PB19 #define PWM1 20 // PB20 #define PWM2 21 // PB21 @@ -291,10 +369,11 @@ #define PWM_PIO_PDR PIOB_PDR #define PWM_PIO_PER PIOB_PER #define PWM_PIO_CODR PIOB_CODR + #define PWM_PIO_SODR PIOB_SODR #define PWM_PIO_OER PIOB_OER #define PWM_PIO_ABSR PIOB_ASR -#elif CPU_ARM_AT91SAM7S256 +#elif CPU_ARM_SAM7S_LARGE #define PWM0 11 // PA11 #define PWM1 12 // PA12 #define PWM2 13 // PA13 @@ -303,6 +382,7 @@ #define PWM_PIO_PDR PIOA_PDR #define PWM_PIO_PER PIOA_PER #define PWM_PIO_CODR PIOA_CODR + #define PWM_PIO_SODR PIOA_SODR #define PWM_PIO_OER PIOA_OER #define PWM_PIO_ABSR PIOA_BSR @@ -316,11 +396,11 @@ * TWI pins definition. *\{ */ -#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#if CPU_ARM_SAM7X #define TWD 10 #define TWCK 11 -#elif CPU_ARM_AT91SAM7S256 +#elif CPU_ARM_SAM7S_LARGE #define TWD 3 //PA3 #define TWCK 4 //PA4 @@ -332,14 +412,14 @@ * ADC pins definition. *\{ */ -#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 +#if CPU_ARM_SAM7X #define ADTRG 18 // PB18 #define AD0 23 // PB27 #define AD1 24 // PB28 #define AD2 25 // PB29 #define AD3 26 // PB30 -#elif CPU_ARM_AT91SAM7S256 +#elif CPU_ARM_SAM7S_LARGE #define ADTRG 18 // PA8 #define AD0 0 // PA17 #define AD1 1 // PA18 @@ -352,4 +432,54 @@ #endif /*\}*/ + +/** + * Pin definition MII/RMII PHY interdace + */ +#if CPU_ARM_SAM7X + #define PHY_TXCLK_BIT BV(0) + #define PHY_TXEN_BIT BV(1) + #define PHY_TXD0_BIT BV(2) + #define PHY_TXD1_BIT BV(3) + #define PHY_CRS_BIT BV(4) + #define PHY_RXD0_BIT BV(5) + #define PHY_RXD1_BIT BV(6) + #define PHY_RXER_BIT BV(7) + #define PHY_MDC_BIT BV(8) + #define PHY_MDIO_BIT BV(9) + #define PHY_TXD2_BIT BV(10) + #define PHY_TXD3_BIT BV(11) + #define PHY_TXER_BIT BV(12) + #define PHY_RXD2_BIT BV(13) + #define PHY_RXD3_BIT BV(14) + #define PHY_RXDV_BIT BV(15) + #define PHY_COL_BIT BV(16) + #define PHY_RXCLK_BIT BV(17) + +#elif CPU_ARM_SAM7S_LARGE + /* No ethernet interface is present on this cpu */ +#else + #error No MII/RMII PHY pins interface was define for select CPU. +#endif + +#define PHY_MII_PINS \ + ( PHY_TXEN_BIT \ + | PHY_TXD0_BIT \ + | PHY_TXD1_BIT \ + | PHY_CRS_BIT \ + | PHY_RXD0_BIT \ + | PHY_RXD1_BIT \ + | PHY_RXER_BIT \ + | PHY_MDC_BIT \ + | PHY_MDIO_BIT \ + | PHY_TXD2_BIT \ + | PHY_TXD3_BIT \ + | PHY_TXER_BIT \ + | PHY_RXD2_BIT \ + | PHY_RXD3_BIT \ + | PHY_RXDV_BIT \ + | PHY_COL_BIT \ + | PHY_RXCLK_BIT) +// \} + #endif /* AT91SAM7_H */