X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Farm%2Fscripts%2Fopenocd%2Fopenocd_new_at91sam7_ftdi_rom.cfg;fp=bertos%2Fcpu%2Farm%2Fscripts%2Fopenocd%2Fopenocd_new_at91sam7_ftdi_rom.cfg;h=ff137cc9999cdb62232622b3b60f5a326fbad64a;hb=6abf03e019383ce5c269318dd72e9d237377cbe5;hp=0000000000000000000000000000000000000000;hpb=388f7931a07e3bf406978bdf788d34e86f33bf53;p=bertos.git

diff --git a/bertos/cpu/arm/scripts/openocd/openocd_new_at91sam7_ftdi_rom.cfg b/bertos/cpu/arm/scripts/openocd/openocd_new_at91sam7_ftdi_rom.cfg
new file mode 100644
index 00000000..ff137cc9
--- /dev/null
+++ b/bertos/cpu/arm/scripts/openocd/openocd_new_at91sam7_ftdi_rom.cfg
@@ -0,0 +1,69 @@
+
+# Change the default telnet port...
+telnet_port 4444
+
+# Port for TCL connection.
+tcl_port 6666
+
+# GDB connects here
+gdb_port 3333
+# GDB can also flash my flash!
+gdb_memory_map enable
+gdb_flash_program enable
+gdb_breakpoint_override hard
+
+interface ft2232
+#ft2232_device_desc "Amontec JTAGkey"
+ft2232_layout jtagkey
+ft2232_vid_pid 0x0403 0xcff8
+
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME sam7
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+
+$_TARGETNAME configure -event reset-init { 
+        # disable watchdog
+        mww 0xfffffd44 0x00008000       
+        # enable user reset
+        mww 0xfffffd08 0xa5000001       
+        # CKGR_MOR : enable the main oscillator
+        mww 0xfffffc20 0x00000601       
+        sleep 10
+        # CKGR_PLLR: 96.1097 MHz
+        mww 0xfffffc2c 0x00481c0e       
+        sleep 10
+        # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+        mww 0xfffffc30 0x00000007       
+        sleep 10
+        # MC_FMR: flash mode (FWS=1,FMCN=60)
+        mww 0xffffff60 0x003c0100       
+        sleep 100
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank at91sam7 0 0 0 0 0