X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fattr.h;h=185da4cc07296ef8eb947adf20c390c2c79cfb0a;hb=6447257f41c6d0f3d6b7a486e2683f930a5afdd3;hp=f54e6b0689e83c436fab62b2b5670dc5200046a0;hpb=42915fdb2ea25ed68b8bb835b78c2bca9b32f1f5;p=bertos.git

diff --git a/bertos/cpu/attr.h b/bertos/cpu/attr.h
index f54e6b06..185da4cc 100644
--- a/bertos/cpu/attr.h
+++ b/bertos/cpu/attr.h
@@ -109,8 +109,8 @@
 	/// Valid pointers should be >= than this value (used for debug)
 	#if CPU_ARM_AT91
 		#define CPU_RAM_START		0x00200000
-	#elif CPU_ARM_LM3S1968
-		#define CPU_RAM_START		0x20000000
+	#elif CPU_ARM_LPC2
+		#define CPU_RAM_START		0x40000000
 	#else
 		#warning Fix CPU_RAM_START address for your ARM, default value set to 0x200
 		#define CPU_RAM_START		0x200
@@ -164,6 +164,31 @@
 		#define RAM_FUNC __attribute__((section(".data")))
 
 	#endif /* !__IAR_SYSTEMS_ICC_ */
+#elif CPU_CM3
+
+	#define CPU_REG_BITS           32
+	#define CPU_REGS_CNT           16
+	#define CPU_HARVARD            0
+
+	/// Valid pointers should be >= than this value (used for debug)
+	#if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32P103)
+		#define CPU_RAM_START 0x20000000
+	#else
+		#warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x200
+		#define CPU_RAM_START 0x200
+	#endif
+
+	#if defined(__ARMEB__)
+		#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+	#elif defined(__ARMEL__)
+		#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+	#else
+		#error Unable to detect Cortex-M3 endianess!
+	#endif
+
+	#define NOP         asm volatile ("nop")
+	#define PAUSE       asm volatile ("wfi" ::: "memory")
+	#define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
 
 #elif CPU_PPC
 
@@ -212,7 +237,7 @@
 	/// Valid pointers should be >= than this value (used for debug)
 	#if CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA32 || CPU_AVR_ATMEGA103
 		#define CPU_RAM_START       0x60
-	#elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA168
+	#elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
 		#define CPU_RAM_START       0x100
 	#elif CPU_AVR_ATMEGA1281
 		#define CPU_RAM_START       0x200