X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fattr.h;h=331f26dff0c372d7290a7e9862b9651ac36dfafc;hb=57fa5e371a8b40afc99b922731b77d17c55330a4;hp=5f5217f03ca3ac3297085411368d95246dd34ef5;hpb=66289a0e7fa93342bc3d8621fa20c5a542807e1e;p=bertos.git

diff --git a/bertos/cpu/attr.h b/bertos/cpu/attr.h
index 5f5217f0..331f26df 100644
--- a/bertos/cpu/attr.h
+++ b/bertos/cpu/attr.h
@@ -178,13 +178,24 @@
 		#define CPU_RAM_START 0x20000000
 	#endif
 
-	#if defined(__ARMEB__)
-		#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
-	#elif defined(__ARMEL__)
-		#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
-	#else
-		#error Unable to detect Cortex-M3 endianess!
-	#endif
+    #if defined( __ICCARM__)
+        #if ((defined __LITTLE_ENDIAN__) && (__LITTLE_ENDIAN__ == 0))
+            #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+        #elif ((defined __LITTLE_ENDIAN__) && (__LITTLE_ENDIAN__ == 1))
+		    #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+        #else
+            #error Unable to detect Cortex-M3 endianess!
+        #endif
+
+	#define NOP            __no_operation()
+    #else
+        #if defined(__ARMEB__) // GCC
+            #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+        #elif defined(__ARMEL__) // GCC
+            #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+        #else
+            #error Unable to detect Cortex-M3 endianess!
+        #endif
 
 	#define NOP         asm volatile ("nop")
 	#define PAUSE       asm volatile ("wfi" ::: "memory")
@@ -194,6 +205,7 @@
 	 * Function attribute to move it into ram memory.
 	 */
 	#define RAM_FUNC __attribute__((section(".ramfunc")))
+    #endif
 
 #elif CPU_PPC
 
@@ -246,6 +258,8 @@
 		#define CPU_RAM_START       0x100
 	#elif CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
 		#define CPU_RAM_START       0x200
+	#elif CPU_AVR_XMEGA
+		#define CPU_RAM_START		0x2000
 	#else
 		#warning Fix CPU_RAM_START address for your AVR, default value set to 0x100
 		#define CPU_RAM_START       0x100
@@ -283,7 +297,7 @@
 
 #ifndef PAUSE
 	/// Generic PAUSE implementation.
-	#define PAUSE	{NOP; MEMORY_BARRIER;}
+	#define PAUSE	do {NOP; MEMORY_BARRIER;} while (0)
 #endif
 
 #endif /* CPU_ATTR_H */