X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fattr.h;h=5f5217f03ca3ac3297085411368d95246dd34ef5;hb=0dce96ca21bcde277a09ecfefa2b798143b57968;hp=5e24fa3c9d3ee7b57ae6d19ad36212f2798789a5;hpb=6a566c9b4ad8efa9ee8432942b85ba31ffb469f8;p=bertos.git

diff --git a/bertos/cpu/attr.h b/bertos/cpu/attr.h
index 5e24fa3c..5f5217f0 100644
--- a/bertos/cpu/attr.h
+++ b/bertos/cpu/attr.h
@@ -109,6 +109,8 @@
 	/// Valid pointers should be >= than this value (used for debug)
 	#if CPU_ARM_AT91
 		#define CPU_RAM_START		0x00200000
+	#elif CPU_ARM_LPC2
+		#define CPU_RAM_START		0x40000000
 	#else
 		#warning Fix CPU_RAM_START address for your ARM, default value set to 0x200
 		#define CPU_RAM_START		0x200
@@ -142,7 +144,7 @@
 			 * to get them transparently copied to SRAM for zero-wait-state
 			 * operation.
 			 */
-			#define FAST_FUNC __attribute__((section(".data")))
+			#define FAST_FUNC __attribute__((section(".ramfunc")))
 
 			/**
 			 * Data attribute to move constant data to fast memory storage.
@@ -159,21 +161,21 @@
 		/*
 		 * Function attribute to move it into ram memory.
 		 */
-		#define RAM_FUNC __attribute__((section(".data")))
+		#define RAM_FUNC __attribute__((section(".ramfunc")))
 
 	#endif /* !__IAR_SYSTEMS_ICC_ */
 #elif CPU_CM3
 
 	#define CPU_REG_BITS           32
-	#define CPU_REGS_CNT           fixme
+	#define CPU_REGS_CNT           16
 	#define CPU_HARVARD            0
 
 	/// Valid pointers should be >= than this value (used for debug)
-	#if CPU_CM3_LM3S1968
+	#if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32 || CPU_CM3_SAM3)
 		#define CPU_RAM_START 0x20000000
 	#else
-		#warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x200
-		#define CPU_RAM_START 0x200
+		#warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x20000000
+		#define CPU_RAM_START 0x20000000
 	#endif
 
 	#if defined(__ARMEB__)
@@ -181,12 +183,18 @@
 	#elif defined(__ARMEL__)
 		#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
 	#else
-		#error Unable to detect Cortex-M3 endianness!
+		#error Unable to detect Cortex-M3 endianess!
 	#endif
 
-	#define NOP         fixme
+	#define NOP         asm volatile ("nop")
+	#define PAUSE       asm volatile ("wfi" ::: "memory")
 	#define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
 
+	/*
+	 * Function attribute to move it into ram memory.
+	 */
+	#define RAM_FUNC __attribute__((section(".ramfunc")))
+
 #elif CPU_PPC
 
 	#define CPU_REG_BITS           (CPU_PPC32 ? 32 : 64)
@@ -207,7 +215,7 @@
 	#define CPU_REG_BITS            16
 	#define CPU_REGS_CNT            FIXME
 	#define CPU_BYTE_ORDER          CPU_BIG_ENDIAN
-	#define CPU_HARVARD		1
+	#define CPU_HARVARD             1
 
 	/* Memory is word-addessed in the DSP56K */
 	#define CPU_BITS_PER_CHAR  16
@@ -236,13 +244,25 @@
 		#define CPU_RAM_START       0x60
 	#elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
 		#define CPU_RAM_START       0x100
-	#elif CPU_AVR_ATMEGA1281
+	#elif CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
 		#define CPU_RAM_START       0x200
 	#else
 		#warning Fix CPU_RAM_START address for your AVR, default value set to 0x100
 		#define CPU_RAM_START       0x100
 	#endif
 
+#elif CPU_MSP430
+
+	#define CPU_REG_BITS            16
+	#define CPU_REGS_CNT            12
+	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
+	#define CPU_HARVARD		        0
+
+	/// Valid pointers should be >= than this value (used for debug)
+	#define CPU_RAM_START           0x200
+
+	#define NOP                     __asm__ __volatile__ ("nop")
+
 #else
 	#error No CPU_... defined.
 #endif