X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fattr.h;h=8232091d719d65066bed618fc228a73b411d5891;hb=ae3571e0d7273f8642468c6a0958c29c05dc7b2a;hp=8fdcb1c8fd2508554809df29b38fbf2158c7fc79;hpb=1e4168b5fc0a9704a37bb8def5e5f90e145b646c;p=bertos.git

diff --git a/bertos/cpu/attr.h b/bertos/cpu/attr.h
index 8fdcb1c8..8232091d 100644
--- a/bertos/cpu/attr.h
+++ b/bertos/cpu/attr.h
@@ -109,6 +109,8 @@
 	/// Valid pointers should be >= than this value (used for debug)
 	#if CPU_ARM_AT91
 		#define CPU_RAM_START		0x00200000
+	#elif CPU_ARM_LPC2
+		#define CPU_RAM_START		0x40000000
 	#else
 		#warning Fix CPU_RAM_START address for your ARM, default value set to 0x200
 		#define CPU_RAM_START		0x200
@@ -169,11 +171,11 @@
 	#define CPU_HARVARD            0
 
 	/// Valid pointers should be >= than this value (used for debug)
-	#if CPU_CM3_LM3S1968
+	#if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32F103RB || CPU_CM3_AT91SAM3)
 		#define CPU_RAM_START 0x20000000
 	#else
-		#warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x200
-		#define CPU_RAM_START 0x200
+		#warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x20000000
+		#define CPU_RAM_START 0x20000000
 	#endif
 
 	#if defined(__ARMEB__)
@@ -185,23 +187,9 @@
 	#endif
 
 	#define NOP         asm volatile ("nop")
+	#define PAUSE       asm volatile ("wfi" ::: "memory")
 	#define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
 
-	/*
-	 * Builtin GCC memset() can be buggy! We need to redefine it here for
-	 * this architecture. :(
-	 */
-	#include <cfg/compiler.h>
-	#define memset	__cm3_memset
-	INLINE void *__cm3_memset(void *s, int c, size_t n)
-	{
-		uint8_t *p = (uint8_t *)s;
-
-		while (n--)
-			*p++ = c;
-		return s;
-	}
-
 #elif CPU_PPC
 
 	#define CPU_REG_BITS           (CPU_PPC32 ? 32 : 64)
@@ -251,13 +239,25 @@
 		#define CPU_RAM_START       0x60
 	#elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
 		#define CPU_RAM_START       0x100
-	#elif CPU_AVR_ATMEGA1281
+	#elif CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
 		#define CPU_RAM_START       0x200
 	#else
 		#warning Fix CPU_RAM_START address for your AVR, default value set to 0x100
 		#define CPU_RAM_START       0x100
 	#endif
 
+#elif CPU_MSP430
+
+	#define CPU_REG_BITS            16
+	#define CPU_REGS_CNT            12
+	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
+	#define CPU_HARVARD		        0
+
+	/// Valid pointers should be >= than this value (used for debug)
+	#define CPU_RAM_START     	    0x200
+
+	#define NOP                     __asm__ __volatile__ ("nop")
+
 #else
 	#error No CPU_... defined.
 #endif