X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fattr.h;h=8b1fa4c7c15e1b99eb7e5a6fedb3958a289ca9bb;hb=88c5c0a97b1bd550d185b9250eaf1a2bcc25e027;hp=832f0618698c724945f7196dfaf97e30cf790404;hpb=32d1445272120a254d77ce8d1af1f527da7a2c17;p=bertos.git

diff --git a/bertos/cpu/attr.h b/bertos/cpu/attr.h
index 832f0618..8b1fa4c7 100644
--- a/bertos/cpu/attr.h
+++ b/bertos/cpu/attr.h
@@ -109,6 +109,8 @@
 	/// Valid pointers should be >= than this value (used for debug)
 	#if CPU_ARM_AT91
 		#define CPU_RAM_START		0x00200000
+	#elif CPU_ARM_LPC2
+		#define CPU_RAM_START		0x40000000
 	#else
 		#warning Fix CPU_RAM_START address for your ARM, default value set to 0x200
 		#define CPU_RAM_START		0x200
@@ -162,6 +164,31 @@
 		#define RAM_FUNC __attribute__((section(".data")))
 
 	#endif /* !__IAR_SYSTEMS_ICC_ */
+#elif CPU_CM3
+
+	#define CPU_REG_BITS           32
+	#define CPU_REGS_CNT           16
+	#define CPU_HARVARD            0
+
+	/// Valid pointers should be >= than this value (used for debug)
+	#if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32 || CPU_CM3_SAM3)
+		#define CPU_RAM_START 0x20000000
+	#else
+		#warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x20000000
+		#define CPU_RAM_START 0x20000000
+	#endif
+
+	#if defined(__ARMEB__)
+		#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+	#elif defined(__ARMEL__)
+		#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+	#else
+		#error Unable to detect Cortex-M3 endianess!
+	#endif
+
+	#define NOP         asm volatile ("nop")
+	#define PAUSE       asm volatile ("wfi" ::: "memory")
+	#define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
 
 #elif CPU_PPC
 
@@ -210,15 +237,27 @@
 	/// Valid pointers should be >= than this value (used for debug)
 	#if CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA32 || CPU_AVR_ATMEGA103
 		#define CPU_RAM_START       0x60
-	#elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA168
+	#elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
 		#define CPU_RAM_START       0x100
-	#elif CPU_AVR_ATMEGA1281
+	#elif CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
 		#define CPU_RAM_START       0x200
 	#else
 		#warning Fix CPU_RAM_START address for your AVR, default value set to 0x100
 		#define CPU_RAM_START       0x100
 	#endif
 
+#elif CPU_MSP430
+
+	#define CPU_REG_BITS            16
+	#define CPU_REGS_CNT            12
+	#define CPU_BYTE_ORDER          CPU_LITTLE_ENDIAN
+	#define CPU_HARVARD		        0
+
+	/// Valid pointers should be >= than this value (used for debug)
+	#define CPU_RAM_START     	    0x200
+
+	#define NOP                     __asm__ __volatile__ ("nop")
+
 #else
 	#error No CPU_... defined.
 #endif