X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fattr.h;h=9840f0f99e8dfcd3d21d18de41764f77c1ea6f2b;hb=e2cdc8384c68cea178b0e585bb4467dae454b449;hp=cb827891dd22839f3f7e97d456f385ff810bd872;hpb=e46395e38dc55069a688bd21d7bf0ed30b8e413e;p=bertos.git

diff --git a/bertos/cpu/attr.h b/bertos/cpu/attr.h
index cb827891..9840f0f9 100644
--- a/bertos/cpu/attr.h
+++ b/bertos/cpu/attr.h
@@ -1,3 +1,4 @@
+advanced = True
 /**
  * \file
  * <!--
@@ -42,6 +43,7 @@
 
 #include "detect.h"
 
+#include "cfg/cfg_proc.h"      /* CONFIG_KERN_PREEMPT */
 #include "cfg/cfg_attr.h"      /* CONFIG_FAST_MEM */
 
 
@@ -94,6 +96,8 @@
 
 	#ifdef __GNUC__
 		#define NOP         asm volatile ("nop")
+		/* This is a good thing to insert into busy-wait loops. */
+		#define PAUSE       asm volatile ("rep; nop" ::: "memory")
 		#define BREAKPOINT  asm volatile ("int3" ::)
 	#endif
 
@@ -106,9 +110,12 @@
 	/// Valid pointers should be >= than this value (used for debug)
 	#if CPU_ARM_AT91
 		#define CPU_RAM_START		0x00200000
+	#elif CPU_ARM_LPC2
+		#define CPU_RAM_START		0x40000000
 	#else
 		#warning Fix CPU_RAM_START address for your ARM, default value set to 0x200
 		#define CPU_RAM_START		0x200
+	#endif
 
 	#ifdef __IAR_SYSTEMS_ICC__
 		#warning Check CPU_BYTE_ORDER
@@ -152,12 +159,37 @@
 			#define FAST_FUNC /**/
 		#endif
 
-		/**
-		 * Function attribute to declare an interrupt service routine.
+		/*
+		 * Function attribute to move it into ram memory.
 		 */
-		#define ISR_FUNC __attribute__((interrupt))
+		#define RAM_FUNC __attribute__((section(".data")))
 
 	#endif /* !__IAR_SYSTEMS_ICC_ */
+#elif CPU_CM3
+
+	#define CPU_REG_BITS           32
+	#define CPU_REGS_CNT           16
+	#define CPU_HARVARD            0
+
+	/// Valid pointers should be >= than this value (used for debug)
+	#if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32F103R8)
+		#define CPU_RAM_START 0x20000000
+	#else
+		#warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x200
+		#define CPU_RAM_START 0x200
+	#endif
+
+	#if defined(__ARMEB__)
+		#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+	#elif defined(__ARMEL__)
+		#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+	#else
+		#error Unable to detect Cortex-M3 endianess!
+	#endif
+
+	#define NOP         asm volatile ("nop")
+	#define PAUSE       asm volatile ("wfi" ::: "memory")
+	#define BREAKPOINT  /* asm("bkpt 0") DOES NOT WORK */
 
 #elif CPU_PPC
 
@@ -206,13 +238,14 @@
 	/// Valid pointers should be >= than this value (used for debug)
 	#if CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA32 || CPU_AVR_ATMEGA103
 		#define CPU_RAM_START       0x60
-	#elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA168
+	#elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
 		#define CPU_RAM_START       0x100
 	#elif CPU_AVR_ATMEGA1281
 		#define CPU_RAM_START       0x200
 	#else
 		#warning Fix CPU_RAM_START address for your AVR, default value set to 0x100
 		#define CPU_RAM_START       0x100
+	#endif
 
 #else
 	#error No CPU_... defined.
@@ -232,4 +265,9 @@
 	#define FAST_RODATA /* */
 #endif
 
+#ifndef PAUSE
+	/// Generic PAUSE implementation.
+	#define PAUSE	{NOP; MEMORY_BARRIER;}
+#endif
+
 #endif /* CPU_ATTR_H */