X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Fattr.h;h=f2183faaa7f7b8bebff271cb5b73b7caca7aba66;hb=84876adb8515eb684c3f076ae9763ca765205951;hp=3fd3b18fbde5d84f3a43a4dc02b764a9e012351a;hpb=c22fe24a0da896a52dbc3882390ec18a440ef56a;p=bertos.git

diff --git a/bertos/cpu/attr.h b/bertos/cpu/attr.h
index 3fd3b18f..f2183faa 100644
--- a/bertos/cpu/attr.h
+++ b/bertos/cpu/attr.h
@@ -44,8 +44,8 @@
 #include "detect.h"
 
 #include "cfg/cfg_attr.h"      /* CONFIG_FAST_MEM */
+#include "cfg/cfg_arch.h"      /* ARCH_EMUL */
 #include <cfg/compiler.h>      /* for uintXX_t */
-#include "cfg/cfg_arch.h"   /* ARCH_EMUL */
 
 
 /**
@@ -115,9 +115,9 @@
 	#else /* GCC and compatibles */
 
 		#if defined(__ARMEB__)
-  			#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
-  		#elif defined(__ARMEL__)
-  			#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+			#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+		#elif defined(__ARMEL__)
+			#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
 		#else
 			#error Unable to detect ARM endianness!
   		#endif
@@ -125,17 +125,17 @@
 		#define NOP            asm volatile ("mov r0,r0" ::)
 
 		/**
-	 	 * Initialization value for registers in stack frame.
-	 	 * The register index is not directly corrispondent to CPU
-	 	 * register numbers, but is related to how are pushed to
-	 	 * stack (\see asm_switch_context).
+		 * Initialization value for registers in stack frame.
+		 * The register index is not directly corrispondent to CPU
+		 * register numbers, but is related to how are pushed to
+		 * stack (\see asm_switch_context).
 		 * Index (CPU_SAVED_REGS_CNT - 1) is the CPSR register,
 		 * the initial value is set to:
 		 * - All flags (N, Z, C, V) set to 0.
 		 * - IRQ and FIQ enabled.
 		 * - ARM state.
 		 * - CPU in Supervisor Mode (SVC).
-	 	 */
+		 */
 		#define CPU_REG_INIT_VALUE(reg) (reg == (CPU_SAVED_REGS_CNT - 1) ? 0x13 : 0)
 
 		#if CONFIG_FAST_MEM