X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Favr%2Fdrv%2Fadc_avr.c;h=51c81caca5d0ee13b9fd3e9304abb40ce56f7484;hb=268d06bb58409df32c2ca35879347336fa13f167;hp=2ba5982fe1da47c477c54474e2999ded7e0b43e4;hpb=70a451db3b503f9984d31e247400fb0dd810e691;p=bertos.git

diff --git a/bertos/cpu/avr/drv/adc_avr.c b/bertos/cpu/avr/drv/adc_avr.c
index 2ba5982f..51c81cac 100644
--- a/bertos/cpu/avr/drv/adc_avr.c
+++ b/bertos/cpu/avr/drv/adc_avr.c
@@ -31,7 +31,6 @@
  *
  * \brief ADC hardware-specific definition
  *
- * \version $Id$
  * \author Francesco Sacchi <batt@develer.com>
  *
  * This module is automatically included so no need to include
@@ -89,7 +88,7 @@
 	 */
 	ISR(ADC_vect)
 	{
-		sig_signal(adc_process, SIG_ADC_COMPLETE);
+		sig_post(adc_process, SIG_ADC_COMPLETE);
 	}
 #endif /* CONFIG_KERN */
 
@@ -97,13 +96,31 @@
  * Select mux channel \a ch.
  * \todo only first 8 channels are selectable!
  */
-INLINE void adc_hw_select_ch(uint8_t ch)
+void adc_hw_select_ch(uint8_t ch)
 {
 	/* Set to 0 all mux registers */
-	ADMUX &= ~(BV(MUX4) | BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
+	#if CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA168
+		ADMUX &= ~(BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
+	#elif CPU_AVR_ATMEGA32 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281 \
+	      || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
+		ADMUX &= ~(BV(MUX4) | BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
+		#if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
+			ADCSRB &= ~(BV(MUX5));
+		#endif
+	#else
+		#error Unknown CPU
+	#endif
 
-	/* Select channel, only first 8 channel modes are supported for now */
+	/* Select channel, only first 8 channel modes are supported */
 	ADMUX |= (ch & 0x07);
+
+	#if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
+		/* Select channel, all 16 channels are supported */
+		if (ch > 0x07)
+			ADCSRB |= BV(MUX5);
+
+	#endif
+
 }
 
 
@@ -112,7 +129,7 @@ INLINE void adc_hw_select_ch(uint8_t ch)
  * If a kernel is present, preempt until convertion is complete, otherwise
  * a busy wait on ADCS bit is done.
  */
-INLINE uint16_t adc_hw_read(void)
+uint16_t adc_hw_read(void)
 {
 	// Ensure another convertion is not running.
 	ASSERT(!(ADCSRA & BV(ADSC)));
@@ -136,7 +153,7 @@ INLINE uint16_t adc_hw_read(void)
 /**
  * Init ADC hardware.
  */
-INLINE void adc_hw_init(void)
+void adc_hw_init(void)
 {
 	/*
 	 * Select channel 0 as default,