X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Favr%2Fdrv%2Fser_avr.c;h=066444822abd40d669fc62ebf41de772ea207af3;hb=38b2221716fa0f648860e1cec14f819daf8cb031;hp=21da6b8eb2f6ea36f334f7e3ad60db9dfca6d67d;hpb=e62ca0b357f09804d7d894949df44224c9d74bb7;p=bertos.git

diff --git a/bertos/cpu/avr/drv/ser_avr.c b/bertos/cpu/avr/drv/ser_avr.c
index 21da6b8e..06644482 100644
--- a/bertos/cpu/avr/drv/ser_avr.c
+++ b/bertos/cpu/avr/drv/ser_avr.c
@@ -664,7 +664,7 @@ struct SerialHardware *ser_hw_getdesc(int unit)
 SIGNAL(SIG_CTS)
 {
 	// Re-enable UDR empty interrupt and TX, then disable CTS interrupt
-	UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+	UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
 	EIMSK &= ~EIMSKF_CTS;
 }
 
@@ -692,7 +692,7 @@ SIGNAL(USART0_UDRE_vect)
 	{
 		// Disable rx interrupt and tx, enable CTS interrupt
 		// UNTESTED
-		UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
+		UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
 		EIFR |= EIMSKF_CTS;
 		EIMSK |= EIMSKF_CTS;
 	}
@@ -733,7 +733,7 @@ SIGNAL(SIG_UART0_TRANS)
 		UARTDescs[SER_UART0].sending = false;
 	}
 	else
-		UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+		UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
 
 	SER_STROBE_OFF;
 }
@@ -763,7 +763,7 @@ SIGNAL(USART1_UDRE_vect)
 	{
 		// Disable rx interrupt and tx, enable CTS interrupt
 		// UNTESTED
-		UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
+		UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
 		EIFR |= EIMSKF_CTS;
 		EIMSK |= EIMSKF_CTS;
 	}
@@ -783,7 +783,7 @@ SIGNAL(USART1_UDRE_vect)
  *
  * \sa port 0 TX complete handler.
  */
-SIGNAL(SIG_UART1_TRANS)
+SIGNAL(USART1_TX_vect)
 {
 	SER_STROBE_ON;
 
@@ -794,7 +794,7 @@ SIGNAL(SIG_UART1_TRANS)
 		UARTDescs[SER_UART1].sending = false;
 	}
 	else
-		UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+		UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
 
 	SER_STROBE_OFF;
 }