X-Git-Url: https://codewiz.org/gitweb?a=blobdiff_plain;f=bertos%2Fcpu%2Favr%2Fdrv%2Fser_avr.c;h=23c4b0760d7f6be343da5843a22caa71b2b66503;hb=e9e5371a9d12d313525fb8ce91886e79f9c7bba2;hp=746bb5270feb6a88eaed545839537975ee4926fe;hpb=6ad5c01d9a3d323e34a547283e7a534f7c3b9d15;p=bertos.git

diff --git a/bertos/cpu/avr/drv/ser_avr.c b/bertos/cpu/avr/drv/ser_avr.c
index 746bb527..23c4b076 100644
--- a/bertos/cpu/avr/drv/ser_avr.c
+++ b/bertos/cpu/avr/drv/ser_avr.c
@@ -26,7 +26,7 @@
  * invalidate any other reasons why the executable file might be covered by
  * the GNU General Public License.
  *
- * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
+ * Copyright 2003, 2004, 2010 Develer S.r.l. (http://www.develer.com/)
  * Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
  *
  * -->
@@ -37,6 +37,7 @@
  *
  * \author Bernie Innocenti <bernie@codewiz.org>
  * \author Stefano Fedrigo <aleph@develer.com>
+ * \author Luca Ottaviano <lottaviano@develer.com>
  */
 
 #include "hw/hw_ser.h"  /* Required for bus macros overrides */
@@ -85,6 +86,16 @@
 	#define BIT_RXEN1  RXEN1
 	#define BIT_TXEN1  TXEN1
 	#define BIT_UDRIE1 UDRIE1
+#elif CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
+	#define BIT_RXCIE0 RXCIE0
+	#define BIT_RXEN0  RXEN0
+	#define BIT_TXEN0  TXEN0
+	#define BIT_UDRIE0 UDRIE0
+
+	#define BIT_RXCIE1 RXCIE0
+	#define BIT_RXEN1  RXEN0
+	#define BIT_TXEN1  TXEN0
+	#define BIT_UDRIE1 UDRIE0
 #else
 	#define BIT_RXCIE0 RXCIE
 	#define BIT_RXEN0  RXEN
@@ -248,7 +259,16 @@
 	#define SPI_SCK_BIT   PB1
 	#define SPI_MOSI_BIT  PB2
 	#define SPI_MISO_BIT  PB3
-#elif CPU_AVR_ATMEGA8
+// TODO: these bits are the same as ATMEGA8 but the defines in avr-gcc are different.
+// They should be the same!
+#elif CPU_AVR_ATMEGA328P
+	#define SPI_PORT      PORTB
+	#define SPI_DDR       DDRB
+	#define SPI_SS_BIT    PORTB2
+	#define SPI_SCK_BIT   PORTB5
+	#define SPI_MOSI_BIT  PORTB3
+	#define SPI_MISO_BIT  PORTB4
+#elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA168
 	#define SPI_PORT      PORTB
 	#define SPI_DDR       DDRB
 	#define SPI_SS_BIT    PB2
@@ -262,6 +282,11 @@
 /* USART register definitions */
 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
 	#define AVR_HAS_UART1 1
+#elif CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
+	#define AVR_HAS_UART1 0
+	#define USART0_UDRE_vect USART_UDRE_vect
+	#define USART0_RX_vect USART_RX_vect
+	#define SIG_UART0_TRANS SIG_UART_TRANS
 #elif CPU_AVR_ATMEGA8
 	#define AVR_HAS_UART1 0
 	#define UCSR0A UCSRA
@@ -270,6 +295,7 @@
 	#define UDR0   UDR
 	#define UBRR0L UBRRL
 	#define UBRR0H UBRRH
+/* TODO: The following SIGs are old style interrupts, must be refactored */
 	#define SIG_UART0_DATA SIG_UART_DATA
 	#define SIG_UART0_RECV SIG_UART_RECV
 	#define SIG_UART0_TRANS SIG_UART_TRANS
@@ -279,6 +305,7 @@
 	#define UDR0   UDR
 	#define UCSR0A USR
 	#define UBRR0L UBRR
+/* TODO: The following SIGs are old style interrupts, must be refactored */
 	#define SIG_UART0_DATA SIG_UART_DATA
 	#define SIG_UART0_RECV SIG_UART_RECV
 	#define SIG_UART0_TRANS SIG_UART_TRANS
@@ -454,9 +481,7 @@ static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct
 	 * - as input but tied high forever!
 	 * This driver set the pin as output.
 	 */
-	#if !(ARCH & ARCH_NIGHTTEST)
-		#warning SPI SS pin set as output for proper operation, check schematics for possible conflicts.
-	#endif
+	#warning FIXME:SPI SS pin set as output for proper operation, check schematics for possible conflicts.
 	ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
 
 	ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
@@ -647,7 +672,7 @@ struct SerialHardware *ser_hw_getdesc(int unit)
 #if CONFIG_SER_HWHANDSHAKE
 
 /// This interrupt is triggered when the CTS line goes high
-SIGNAL(SIG_CTS)
+DECLARE_ISR(SIG_CTS)
 {
 	// Re-enable UDR empty interrupt and TX, then disable CTS interrupt
 	UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
@@ -660,7 +685,7 @@ SIGNAL(SIG_CTS)
 /**
  * Serial 0 TX interrupt handler
  */
-SIGNAL(USART0_UDRE_vect)
+DECLARE_ISR(USART0_UDRE_vect)
 {
 	SER_STROBE_ON;
 
@@ -708,7 +733,7 @@ SIGNAL(USART0_UDRE_vect)
  * otherwise we'd stop the serial port with some data
  * still pending in the buffer.
  */
-SIGNAL(SIG_UART0_TRANS)
+DECLARE_ISR(SIG_UART0_TRANS)
 {
 	SER_STROBE_ON;
 
@@ -731,7 +756,7 @@ SIGNAL(SIG_UART0_TRANS)
 /**
  * Serial 1 TX interrupt handler
  */
-SIGNAL(USART1_UDRE_vect)
+DECLARE_ISR(USART1_UDRE_vect)
 {
 	SER_STROBE_ON;
 
@@ -769,7 +794,7 @@ SIGNAL(USART1_UDRE_vect)
  *
  * \sa port 0 TX complete handler.
  */
-SIGNAL(USART1_TX_vect)
+DECLARE_ISR(USART1_TX_vect)
 {
 	SER_STROBE_ON;
 
@@ -804,7 +829,7 @@ SIGNAL(USART1_TX_vect)
  *       RXCIE is cleared.  Unfortunately the RXC flag is read-only
  *       and can't be cleared by code.
  */
-SIGNAL(USART0_RX_vect)
+DECLARE_ISR(USART0_RX_vect)
 {
 	SER_STROBE_ON;
 
@@ -852,9 +877,9 @@ SIGNAL(USART0_RX_vect)
  * is heavily loaded, because an interrupt could be retriggered
  * when executing the handler prologue before RXCIE is disabled.
  *
- * \see SIGNAL(USART1_RX_vect)
+ * \see DECLARE_ISR(USART1_RX_vect)
  */
-SIGNAL(USART1_RX_vect)
+DECLARE_ISR(USART1_RX_vect)
 {
 	SER_STROBE_ON;
 
@@ -895,7 +920,7 @@ SIGNAL(USART1_RX_vect)
 /**
  * SPI interrupt handler
  */
-SIGNAL(SIG_SPI)
+DECLARE_ISR(SIG_SPI)
 {
 	SER_STROBE_ON;